Solartron 7071 / 7081 last digit is jumping all over the place

[Mickle T.]

There is another part of ADC: forcing waveforms switch IC307.

[picburner]

In my 7081, as well as other failures, I also found a leaky C201 (100nF 200V 1%) which gave me a random  instability on the latest digits.
Measured with a multimeter it looked good but it was leaky under a more high voltage.
The replacement, in my case, has solved the defect.

[e61_phil]

In my 7081, as well as other failures, I also found a leaky C201 (100nF 200V 1%) which gave me a random  instability on the latest digits.
Measured with a multimeter it looked good but it was leaky under a more high voltage.
The replacement, in my case, has solved the defect.

That sound interesting! What kind of capacitor do you use as a replacement?
I have some 100nF MKS caps here. Might they work?

There is another part of ADC: forcing waveforms switch IC307.

Ah, ok it looks like another switching between the references. I will have a look with the scope.

[Kleinstein]

C201 is the main integrating capacitor. So it should be low loss for highest accuracy / linearity. So MKS might be Ok for a first test, but the proper type would be MKP or similar.

The trouble could be not only leakage, but also increased loss due to humidity / delamination.

[e61_phil]

I replaced C201 with a 100nF 63V MKS (a fraction in size of the original C201) and the noise is still the same. Perhaps, this very small MKS is a bad replacement or there is another problem.

I had a brief look at IC307 and it looks ok. I will check jitter later.

[Kleinstein]

A MKS cap might be just as bad as an MKP that got to much humidity inside. So I would keep that capacitor in mind. A new MKP type might be quite large, as 200 V types are not that common.

Doing a few noise tests at different integration times might also help and give a clue.

[e61_phil]

Doing a few noise tests at different integration times might also help and give a clue.

I made some tests with different number of digits. It seems to be in every mode the last digit is noisy. Or is there another way to change the integration time?


IC202 has now a socket with a new LM301 installed. But still nothing changes..

Is it normal that one can see the GLUG switching at many places? Perhaps the caps around IC205 are gone bad? I will have a look at C213 (47µF).

[Mickle T.]

Is it absolutely normal that you can see the GLUG switching at many places. The input amplifier MDM channel and ADC are fully synchronous, so there is no problem.

[wiss]

Is IC404 stable?

[e61_phil]

Is it absolutely normal that you can see the GLUG switching at many places. The input amplifier MDM channel and ADC are fully synchronous, so there is no problem.

Yes, a 22µF in parallel to C213 didn't changed anything. As you mentioned.

Is IC404 stable?

I haven't measured IC404 directly but the whole chain from the input jacks to the ADC input (measured with HP 3456A on R201) seems to be stable. And I opened SP501 and injected a signal directly into the ADC. That was also noisy.

[Kleinstein]

The testpoint TP202 / TP203 might be interesting to see if switching of the FETs is really working as supposed.

Another option for fault finding might be using hot or cold air to test components / circuit parts. Faulty parts may be more sensitive to temperature / tapping.

The caps at U205 are just part of the digital supply - one could check the noise at the supply to see if there is to much noise there.

If all is working perfectly, I would expect one main noise source to be the LM301 of the integrator. Low frequency voltage noise is set by the chopper OP, but current noise of the OP should be significant for all frequencies, and the 100 K resistors at the input are rather high impedance. Though a long shot, it might be worth a try to do a upgrade with this OP to a low noise JFET based OP, like OPA134 or OPA140. Pin 1 would be left open, as these OPs are internally compensated.

[e61_phil]

The testpoint TP202 / TP203 might be interesting to see if switching of the FETs is really working as supposed.

Ok, anything I should have a closer look on? The damn thing with this meter is: It works except these noisy last digits. So it is very hard to see any fault with the scope.

Another option for fault finding might be using hot or cold air to test components / circuit parts. Faulty parts may be more sensitive to temperature / tapping.

I've tried that already with coolant spray (or whatever "Kältespray" in english is..) but it is very difficult to see anything. Every time the offset increases, in cause of ice out of the air humindity and this ice will melt and leave water on the pcb. Unfortunately, I have no equipment to apply hot air on a small region.

If all is working perfectly, I would expect one main noise source to be the LM301 of the integrator. Low frequency voltage noise is set by the chopper OP, but current noise of the OP should be significant for all frequencies, and the 100 K resistors at the input are rather high impedance. Though a long shot, it might be worth a try to do a upgrade with this OP to a low noise JFET based OP, like OPA134 or OPA140. Pin 1 would be left open, as these OPs are internally compensated.

I'll keep this in mind . I think there is much room for improvements as Mickle showed. My favorit opamp for low noise, low input current stuff with some GBW is the ADA4817 (haven't checked the specs against your candidates for this application)

[e61_phil]

Some further measurements...

I had a closer look to the forcing waveform. I've measured between C212 and R221 (yellow) and Pin 9 of IC833 (blue). Or rephrased: Blue is the driving signal of IC307 and yellow is the AC coupled output.

The falling edge looks fine but the rising edge showed some jitter. The jitter seems to be around 50ns. Could that cause my problems?

I think the jitter is too small to cause the problems. Periodtime of 160Hz ist 6.25ms. And 50ns is only 8ppm of 6.25ms. And one 6.5 digit measurement lasts 400ms. So 64 times 6.25ms. The square root of 64 is 8. This should reduce the 8ppm jitter to 1pmm, I think.


I had also a brief look at TP204 against TP203. It looks fine. No jitter at all. For measurements at TP202 I have to desolder the 22µF next to C213 first. But it is too late for soldering today

PS: Blue is 2V/Div not 20

[Kleinstein]

The forcing waveform should not show any significant jitter. It is derived from the PLL signal, so it really be stable to maybe +-5 ns. Especially if jitter is only for one slope, this is suspicious, as noise from the PLL would effect both sides. So this is definitely a point to look at. It could be either IC307 or just decoupling of that chip and less likely the driving level or ground.

Noise on the forcing waveform might have quite a big effect, as the forcing waveform is coupled rather strong to the integrator with 40 K resistance, compared to 100 K for the signal and refference.

The  ADA4817 is very good at high frequencies, but not that good at lower frequencies. It's also rather fast and might not be stable in such a circuit. The OPA140 is a JFET OP with exceptionally low noise in the LF region. So while higher noise at 100 kHz, it's much better at 100 Hz. Also the OPA140 is not that fast (still faster than LM301) and ins available in DIP.

[e61_phil]

The forcing waveform should not show any significant jitter. It is derived from the PLL signal, so it really be stable to maybe +-5 ns. Especially if jitter is only for one slope, this is suspicious, as noise from the PLL would effect both sides. So this is definitely a point to look at. It could be either IC307 or just decoupling of that chip and less likely the driving level or ground.

My measurements shows only jitter from IC307 (input -> output). The scope was triggered to the forcing waveform. Therefore, the jitter from the forcing waveform itself isn't shown. I will do some jitter measurements on the forcing waveform itself later.

Noise on the forcing waveform might have quite a big effect, as the forcing waveform is coupled rather strong to the integrator with 40 K resistance, compared to 100 K for the signal and refference.

Shouldn't it affect the measurement only relative? So x ppm Jitter should only result in x ppm noise without any relative amplification?

[Kleinstein]

The forcing part is added with a smaller resistor, so about 2,5 times (40 K vs 100 K resistance) the amplitude as a normal signal. So the +-10 V forcing signal will look like a +-25 V signal at the signal input.
So as a first approximation a 1 ppm error due to jitter in forcing waveform could have a 2.5 ppm (of full scale) on the output. It gets even a little more complicated, depending at which time the integration is ending. Also the forcing signal is AC coupled, which should reduce the effect, but occasional jitter will include components at frequencies below sampling frequency. So I would expect the noise due to this problem to go down faster than sqrt(time) with longer integration time. Still the jitter effects can show correlation over time making it difficult to estimate the error.

For only 50 ns Jitter I would also expect less noise, but who knows how the scope probe might influence the circuit.
But at least the jitter from the control input of U307 to outputs of U307 shows that there is very likely something wrong with this chip - there may be more trouble (e.g. higher resistance, charge injection) than just the jitter.

I would not expect much jitter with the controlling digital signal, but you never know. Jitter of the forcing signal should be better visible before the capacitor, as this would include less effect from the integrator part.

[e61_phil]

I've tried to measure the jitter on the forcing waveform itself. It seems to me, that there is a huge jitter. But it is next to impossible to measure, cause of the instability of the frequency (which is related to the mains 50Hz instability)

[e61_phil]

And the story goes on..

To be able to measure the jitter on the forcing waveform I cut pin 6 of IC834, which gives the line frequency. At this point I fed in stable 50Hz out of my function generator.

The jitter in periodtime on the forcing waveform is quite large with about 300ns.


Edit: I saw my Siglent SDG1025 function gen generates a lot of jitter on the 50Hz output. I swapped to my HP 8165A, which also creates some jitter but far less than the siglent. With the HP generator the jitter of the forcing waveform is reduced to approximately 100ns. With this setup the Test0 noise is nearly halfed from 11µVpp to 6µVpp. This seems to be the right way. But I thought the PLL circuit should reduce the incoming jitter quite a lot?

But what can be the problem with the mains frequency? This frequency drifts around but should have no jitter.


Edit2: I kept it running and now I'm not sure if the noisy is really improved.

[Mickle T.]

Mains 50Hz instability is a reason why I kill PLL in two of the three my 7081's.
Datron 1271 disables the PLL's voltage control input during the most sensitive phase of conversion. Datron 1281 have no PLL at all.

[e61_phil]

Mains 50Hz instability is a reason why I kill PLL in two of the three my 7081's.
Datron 1271 disables the PLL's voltage control input during the most sensitive phase of conversion. Datron 1281 have no PLL at all.

I heard about your modification. Do you create a new 60Hz signals or direct 5.24 MHz? And is it enough to feed 5.24MHz into the CLK net (pin 5 of IC835) or is it neccessary to be within phase with the signal which comes out of IC834 pin 6?

[Mickle T.]

7081(#1) have a TCXO 10485 kHz, connected to pin 3 of IC835 (trace to R816, TR807 was cuted). 7081(#2) have a programmable  silicon MEMS based CMOS oscillator 5242.8 kHz, connected to the trace from pin 5 of IC835 (pin is disconnected).

[e61_phil]

Thanks Very interesting. It would be fun to improve the meter later, but at first it should run as proposed by Solartron.

But, for further testing I will disconnect pin 5 from IC835 and feed in 5.24MHz out of a function gen. But this will drive IC824 into saturation, I think. Furthermore, the chain from mains all the way down to the 10Hz output from IC820 will stay coupled with the mains frequency (and no longer in phase with the 5.24MHz).

These long term Test0 measurements, were they done with a modified 7081 or with your third unmodded device?

[Mickle T.]

Both (modded and unmodded) shows ~ the same results in TEST0.

[Kleinstein]

Ideally the PLL will reduce the Jitter from the line frequency somewhat, at least the higher frequency part.  Still this is not easy, as it take quite long filtering times / stable VCO, which are not easy to realize.  Lots of solar power and some wind power might give additional jitter to the line frequency - so things might have worked better 20 years ago.

It is possible that the PLL is not perfectly working. This could be something like a capacitor in the PLL filter lost capacitance, or also the "sine" to pulse conversion of the line signal (switched modes supplies could add noise here). The line frequency is not perfect, but also not that bad. So it might take a good PLL to get a stable clock from this. With the changes grid this might need improvements / modifications to the original PLL.

For first test a fixed frequency instead of the PLL is a good idea: residual 50 Hz coupling would than result in a very low frequency essentially single frequency background that is easy to distinguish from noise.

[e61_phil]

Today I cut the VCO from IC835 and fed 10.48576 MHz into pin 3 of IC835. Now, all jitter is gone. The force waveforms looks perfect and also the GLUG signals. Only one discrete 200ns timestep was seen on the GLUG signals. But that will correspond to the 5MHz clock.

And what happend to the noise? NOTHING!


I recap what is done until now:

- Power Supplies seems to be ok
- PLL voltage trimmed to 2.5V
- Input chain from bindung posts to the Integrator input seems to be ok -> it should be an ADC problem
- direct signal injection in the ADC shows noise and also Test0 mode -> more arguments for an ADC problem
- IC201 was replaced by a new one
- IC202 was replaced by a new one
- caps were added over IC202 to stabilize power supply
- zener voltage from D204 and D205 is stable
- C201 was replaced with a 100nF MKS -> no change at all
- TR201 and TR202 were swapped with others from others circuits
- TR203 and TR204 were swapped with others from other circuits
- 50Hz mains signal was replaced with 50Hz from signal gen to avoid drifting
- PLL circuit was disabled an 10.48576 MHz was fed in IC835 to remove jitter

There is still more than 10µVpp noise within 60s measurement with 7.5 digits

I think there is not much left to try? Perhaps, IC203, IC204 and IC205 Only these remain in the ADC circuit.