Today I used my HP 8165A to feed 10.48MHz (no more resolution available on the HP 8165A) into pin 3 of IC835. Afterwards the drift is gone but it is still noisy.
The noise is even a bit higher as with the real ADC? So I don't know how to interpret this. The noise within 200 6.5 digit measurements is now about 51µV RMS and 280µVpp.
Edit:
To get -1V instead of 0V on the Solartron I have to reduce the pulse width by about 200ms. Therefore, a change of 10µV needs a change of 2µs in pulse width. I've measured the pulses from the siglent and the jitter is in the region auf 10ns. So far too small to induce this noise. The 10.48MHz out of the HP gen aren't that stable, but I think that isn't a big problem, cause the HP generates the "master clock" with the force waveform which is then synced with the siglent.
Edit 2:
I saw a ~100ns jitter on the GLUGS signal and the ~5MHz signal at pin 9 of IC205 is also jittering/drifting 1.5ms after the force signal edge. So I decided to get rid of the HP 8165A and use my 10MHz DOCXO. I think 10.48 or 10.0MHz shouldn't matter anything because in the digital part we don't have to reduce any mains frequency related noise.
After some breadboarding to get a TTL signal out of the DOCXO the noise is gone
(not tested with the real ADC yet!). Also the 200ns jitter in the GLUGS signal is gone.
Edit 3:
I kept the DOCXO for the clock an resoldered SP201 and SP202. The noise is still the same
One can see know again these 200ns jitter on the GLUGS signals. Perhaps it may cause more issues than expected?