Solartron 7071 / 7081 last digit is jumping all over the place

[wiss]

I do not like the ragged part after 200 s but I can not say that it is wrong.
The PLL in my 7075 is similar, I could take a look after the weekend, unless someone can post that voltage from a working 7081.

[Kleinstein]

With the measurement done at fix clock, the PLL is essentially out as a noise source. Though a not so stable clock from the generator might be a problem.

I know that the Comparators and IC307 for the forcing signal is already changed, but these two circuit areas are still the two main suspects to me.

For the forcing waveform this could still the signal level that goes to IC307 - going from TTL to CMOS is sometime just on the edge of working for the high level. But if this is a problem is should be visable as jitter (something like 100-1000ns) at the forcing waveform - thus much more than expected from the chip (e.g. 1 ns level).

For the comparators there are a few possible causes for trouble: The noise of the LM311 is usually not specified and not all manufacturer might give chips that are really good here. The second part is the supply. The hysteresis part adds some portion of the supply back - so this part could be very sensitive to noise on the supplies. The negative supply is somewhat coupled to ground via C223. Thus adding caps directly to the supply might couple noise to this ground and though good for the chip, might cause trouble too. The other supply that enters is the negative 10 V - that might contain some HF noise from the TTL chips also using this. One test here could be using a larger hysteresis (e.g. 10 K parallel to R217/R218) - if the supply noise coupled though R217/R218 is a problem, the noise should get larger by about a factor of 3 from this.

[wiss]

My 7075 has ~10 mV sub-second variations on the control-voltage for the PLL and the 3.2 MHz varies about 1 kHz on the same times-cale.

Red curve is the control voltage green the frequency.

First picture is control voltage and pll-frequency.

Second picture is control voltage and 50 Hz (sync) frequency.

First time I hooked up my counter to the GPIB-system

[e61_phil]

With the measurement done at fix clock, the PLL is essentially out as a noise source. Though a not so stable clock from the generator might be a problem.

I know that the Comparators and IC307 for the forcing signal is already changed, but these two circuit areas are still the two main suspects to me.

For the forcing waveform this could still the signal level that goes to IC307 - going from TTL to CMOS is sometime just on the edge of working for the high level. But if this is a problem is should be visable as jitter (something like 100-1000ns) at the forcing waveform - thus much more than expected from the chip (e.g. 1 ns level).

For the comparators there are a few possible causes for trouble: The noise of the LM311 is usually not specified and not all manufacturer might give chips that are really good here. The second part is the supply. The hysteresis part adds some portion of the supply back - so this part could be very sensitive to noise on the supplies. The negative supply is somewhat coupled to ground via C223. Thus adding caps directly to the supply might couple noise to this ground and though good for the chip, might cause trouble too. The other supply that enters is the negative 10 V - that might contain some HF noise from the TTL chips also using this. One test here could be using a larger hysteresis (e.g. 10 K parallel to R217/R218) - if the supply noise coupled though R217/R218 is a problem, the noise should get larger by about a factor of 3 from this.

Today I desoldered the 1µF caps from the LM311s and put 10k in parallel with R217 and R218. The measured noise was 16µV RMS and without these resistors it was the same.

I also measured the forcing waveform drive signal against pin 4 of IC307. There was no jitter.

[Kleinstein]

Today I desoldered the 1µF caps from the LM311s and put 10k in parallel with R217 and R218. The measured noise was 16µV RMS and without these resistors it was the same.

I also measured the forcing waveform drive signal against pin 4 of IC307. There was no jitter.

So this would exclude two more possible error sources.

There still is the question whether the noise is due to a defect (parts well out of specs) or just due to the normal design weakness and possibly parts at the lower end of specs. Remember that the 7071 is the less tightly tested / lower spec version.

For me the main suspects would be the comparators switching at the wrong time sometimes.  I don't expect the LM311 to be so noisy - my rough estimate would give something like a 100 ns uncertainty, which would be something like a +-1 count. So some contribution (e.g. 0.2 ppm for the 6 digit more), but not much.  But one never knows - it's a low cost part made by many sources, and not all have exactly the same specs. Though chances are low, one could test different LM311 chips.

Another point might be noise on the ground line 0V(s)1 , from C223 to ground. If there is more noise than expected on the supply (+15V) this could get coupled here. To me the supply decoupling around IC202,IC203,IC204 does not look very good solved. usually not having local decoupling on a LM311 is a bad sign, but if there this might couple noise to a sensitive ground line. For me the logical solution would have been having a kind of resistor/inductance in the positive supply and than have local decoupling.

 

[e61_phil]

I still can't believe that this meter will be in spec. It will be a complete useless 6.5 digit meter. Unfortunately, I only found noise limits for the 7081.

Perhaps I should think about a test circuit for the LM311.

What do you think about removing IC202 and fed a voltage from a calibrator into TP201 (Integrator) and look at the comparators output? I can record the hysteresis (hopefully).

Another test could be a puls from a function generator into TP201 to measure the jitter of the LM311.

[wiss]

I still can't believe that this meter will be in spec. It will be a complete useless 6.5 digit meter. Unfortunately, I only found noise limits for the 7081.

the older 7075 is spec'd to +- 1 count at 1 s integration for 10 readings and 10 V in, I can not believe that the 7071 is worse than that...

[Kleinstein]

To check for jitter from the LM311, one could trigger the scope on the output of the LM311 and look at the input signal. This could be tricky, as the voltages are really small, so a normal scope will not see much. The trouble is there is not that much noise needed to upset the comparators. The integrator output is rather lowly changing (e.g. 250 V/s) so it only takes some 250 µV to delay the comparator by 1 µs. This rather small signal will be problem with a separate test jig too.

One way to exclude / reduce noise from the comparators would be to give them an amplified signal. E.g. have a small amplifier (e.g. 10 fold amplification for small signals, down to 1 for a large signal) between IC202 and the comparators. This addition might be easier than an extra test jig for the comparators. 

It might also be interesting to have the scope triggered from the forcing signal and look at the outputs of the comparators. Ideally there should be not more than about 100-200 ns of variations due to the clocked feedback.

From looking at the counter in the digital section, I can no see (at least if the circuit is as in the plan, they could have done different !) a way a mistake there would add noise to individual conversions, but not effecting the long time average.

It might be a good idea to check the old data again, by plotting a histogram. The distribution of values might give more clues about the origin of the errors - could be still a few measurements that are off by a lot or more normal noise.

It might also help to compare the noise in the 5 digit mode. Here the date are from shorter times and thus might show the trouble even stronger. The higher forcing frequency might give some more information. Here it should also be more clear if the noise is really to high.

With the 5 digit mode one could also do a test on the effect of the forcing waveform. With a smaller resistance (e.g. 22 K in parallel) for R221 one would get a stronger forcing signal. This should result in more noise if the forcing part is the problem. It's difficult to do the test in 6 digit mode, as the integrator might saturate.

[e61_phil]

Unfortunately, I had no time the last days for further measurements. However, I read a post in the volt-nuts mailinglist about the difference between the 7071 and 7081. The message was: only the frontpanel and the reference diode selection will differ. The best reference diodes went into the 7081 and the others went into 7071 models.

Furthermore, I asked one to measure the Peak-Peak noise in the 10V range in 6.5 digit mode on his 7071 (he hasn't any GPIB or RS232 cables). And he measured 60µVpp in about 40min. This result isn't much better than mine.

Perhaps Kleinstein is right with his idea that this noise could be in spec for a 7071?

Could anyone with a 7071 reproduce this test?

And could it be the case, that this increased noise is induced by a worser reference zener? Or is it more likely, that other parts are also worse in a 7071 meter (by selection)?

[Kleinstein]

More noise from the reference diode is unlikely to have much influence on the readings with shorted input / reading zero. Due to the forcing signal, the noise in the 160 Hz Band of the reference can still have some influence. As this is higher than the typical 1/f noise region, so only a really noisy reference would give so much noise that it would really be visible. Something like a 100 nV/Sqrt(Hz) noise (e.g. about what a LM399 or LM329 have) from the reference would cause something like 0.8 - 1 µV_pp for the 400 ms integration time of the 6 digit mode.  Noise of zener diode varies a lot, but it would need a really noisy one to get in the 50 µV region. Also the noise would have a more or less white spectrum. Thus does not match the observed FFT.

The noise spectrum looks like the noise is somewhere in the timing of the comparators. So the observed noise is expected to be considerably worse in the 5 digit more and not that bad in the 7 / 8 digit mode. Doing a short calculation gives a not so small contribution for the noise from the LM301 and LM311. The LM301 is specified at about 15 nV/Sqrt(Hz). The LM311 has comparable bias and thus is expected to have a similar, maybe slightly lower noise. So together this is something like 20-25 nV/Sqrt(Hz). The bandwidth should be somewhere in the 10-15 MHz region, again a little hard to estimate. This would give a 60-80 µV_rms noise for the trigger level. At a slope of about 200 V/s this would correspond to something like a 0.2-0.4 µs jitter for the comparator. For a 0.4 s integration time and jitter at both ends this could give a noise in the 1 ppm = 10 µV_RMS range. So peak-peak values of 50-60 µV sounds reasonable and to a large part explainable to the noise of these two chips.

I don't expect so much scattering in the quality of the LM301 and LM311, even though the LM311 usually has no noise specs. The good thing is that it might be easy to test an upgrade to the LM301 by just drop in of a better OP (leave pin 1 open). The LM301 is not that bad, but there are modern JFET based OPs with lower noise. For a test even OP27/LT1007 would be an option - current noise might be a problem for the 8 digit mode.  If you order parts, one might also consider testing a different manufacturer for the LM311 - they are not expensive.  One could also do a test using a slightly smaller (or larger) integration cap (e.g. 68/200 nF instead of 100 nF) - this should reduce (or increase)  the noise from the LM301 and LM311s, though may increase settling time and nonlinearity.

[barnacle2k]

I fully characterized the noise on my Solartron for the DMM noise thread, the results should be somewhere in there. (all ranges all, all digits)

Noise for 10V range and 6.5 digits was 23.5uVpp, measuring window ~40minutes (6000 samples) .

[e61_phil]

I fully characterized the noise on my Solartron for the DMM noise thread, the results should be somewhere in there. (all ranges all, all digits)

Noise for 10V range and 6.5 digits was 23.5uVpp, measuring window ~40minutes (6000 samples) .

Thanks I will have a lokk into the DMM noise thread.

But, how can you measure 23.5µVpp with a resolution of only 10µV?

[Mickle T.]

This is the average value over 6000 samples. IMHO for a such long interval peak-to-peak measurement is almost useless due to thermal drift e.t.c.

[barnacle2k]

In 10V 6.5digit mode there is no visible drift in that timeframe.
There are only 4 discrete values in the data.

I used floating point output format over rs232. 
All my data can be found as CSV's on TiN's ftp if you want to analyze it yourself.

Code: [Select]

ftp://datashort:datashort@ftp.xdevs.com/barnacle2k

[e61_phil]

In 10V 6.5digit mode there is no visible drift in that timeframe.
There are only 4 discrete values in the data.

I used floating point output format over rs232. 
All my data can be found as CSV's on TiN's ftp if you want to analyze it yourself.

Code: [Select]

ftp://datashort:datashort@ftp.xdevs.com/barnacle2k

Thanks! Very interesting data.

Has anyone with a 7071 (not 7081) a similiar data set? (10V range would be sufficient)

[e61_phil]

Today, I want to do some drift measurements and I though "switch the filtering on and ignore the noise at first". The filtered measurement looks fine until the meter readjust the zero

[wiss]

How does the 7081 auto-null? I can not find any breaks in the input circuit...

Edit:
By opening RL5 and closing RL4?
Does RL4 close properly?

[e61_phil]

How does the 7081 auto-null? I can not find any breaks in the input circuit...

Edit:
By opening RL5 and closing RL4?
Does RL4 close properly?

I would think it measures zero by closing TR516 and TR517 like in Test0 Mode. And if it takes only one measurement for zero, the unfiltered noise will be added to the signal. That would explain the steps in the signal.


I've also attached a FFT measured in 5.5 digit mode (~32000 samples). I've averaged the sampling time, because due to the PLL the sampling time isn't excatly 100ms all the time (+/- 5ms).

[wiss]

I would think it measures zero by closing TR516 and TR517 like in Test0 Mode. And if it takes only one measurement for zero, the unfiltered noise will be added to the signal. That would explain the steps in the signal.

Thanks!

I've also attached a FFT measured in 5.5 digit mode (~32000 samples). I've averaged the sampling time, because due to the PLL the sampling time isn't excatly 100ms all the time (+/- 5ms).

Your line frequency varies by +-5%?

[Kleinstein]

The observed noise at  e61_phil's DMM agian shows the strange increase to higher frequencies also in 5 digit mode.  As expected the amplitude is comparable when comparing the same frequency. So the higher forcing frequency at least does not make things much worse. The data values are correlated and the filtering is thus more effective than normal (e.g. with white noise) to suppress the noise. So no surprise to find quite good data after filtering.

The data show something like 3-5 times the noise as the data from barnacle2k - assuming these data are measured without filtering. At least for the higher resolution modes ( 7 and 8 digits)  there could be minor differences in the software that might lead to slightly lower noise due to a subtile form of filtering.
It might still be interesting to see a FFT of these data, especially the 6 digit mode, to see if they show the same correlation. It might be a little difficult to see, as the quantization noise is of similar size.

Form the PDF linked above, one possible problem might be due to to little forcing signal - this might make the integrator plus PWM feedback part not getting fully stable. One could test this with something like a 10% more forcing (e.g. 390 K in parallel to R221). Other Solartrons even have a pot to adjust the forcing strength to find an good value - so maybe this one is just ad the edge.


5% variations would be way to much for the PLL. Is this real, or just a problem in measuring the time data are coming in ?

[wiss]

I saw data for the variations https://en.m.wikipedia.org/wiki/Power_quality, this agrees with what I saw myself, maybe +- 0.2 Hz variation,  no way as high as +-2.5 Hz. I measured with a 10 ms gate-time.

Edit:
Here is data, 10 ms gate-time on the counter, x-axis in seconds.

[e61_phil]

I've measured the 160Hz signal in https://www.eevblog.com/forum/metrology/solartron-7071-7081-last-digit-is-jumping-all-over-the-place/msg885093/#msg885093
The variation was about 1000ppm.

The sampling time measurement is done by labview. Normaly it is stable to about 1ms. I also tried the same VI with my HP 3456A and I can go down to 15ms and it is stable to 1ms. Perhaps, this is no issue and only a different way of data communication? In LabVIEW I measure the time between two instrument readings. Unfortunately, there is no VMC (volt meter complete) output like on HP DMMs. I will test it tomorrow with a clock out my function gen.

The meter gets quite warm inside if you run it closed. Is that normal? It think the electronic under this PCB shield (digital stuff) reaches about 40°C.

I will test the stronger forcing signal tomorrow.

Another thing was the foldback amplifier. Doesn't it decrease the linearity? And what about more modern comparators? I think I will give up with finding the error without changing anything on the original circuit. I think it is time for modern improvements. What is your opinion?

I also measured the 10V reference. There is plenty of distortion from anything correlated with the forcing frequency (but shifted in time). Are you sure that will cancel out completely? Is it perhaps worth to desolder TR301 and feed in 10V from my Fluke 343A into TP302?

[Kleinstein]

The extra amplifier between integrator and the comparators should not have much effect on linearity. It is more like a way to improve the GBW and thus speed of the comparators and replace the noise of the comparator with the better defined noise of the amplifier.  As a side effect there will be a reduced noise bandwidth / filtering of really high frequency noise. So also some of the noise from the LM301 could be reduced by limiting the bandwidth.

With amplification R215 and maybe R214 should get larger to.

Only at the very extremes (e.g.  more than 9.99 V in the 10 V range) the switching of the comparator might be relatively close the switching of the forcing signal and thus a delay from the amplifier could have a small negative effect on linearity. The longer the integration time, the less important this very last switching moment gets - so no real deal for 7 and 8 digit modes. Except just after switching the output of the integrator is a rather low slew rate (e.g. 300 V/s) signal. So the amplifier does not have to be really fast.

Using more modern comparators is tricky: most use lower supply. Also a faster comparator will be sensitive to higher frequency noise. So faster is not better in this respect. The only advantage might be from having a build in hysteresis instead of the added in AC feedback - but the test showed no big problem with this. After amplification I see not problem with using a LM311.

Another possible improvement could be RC filtering (e.g. 5K 1µ) at the reference (at pin 2 of IC305). This could reduce the 160 Hz band noise, though likely not a really big deal, unless the reference is really noisy.

[barnacle2k]

The data show something like 3-5 times the noise as the data from barnacle2k - assuming these data are measured without filtering.

The digital filter mode on the DMM was not active.

It might still be interesting to see a FFT of these data, especially the 6 digit mode, to see if they show the same correlation. It might be a little difficult to see, as the quantization noise is of similar size.

My data looks similar when put through an FFT.

[e61_phil]

Is there a simple but sufficient example for a foldback amplifier available anywhere?