Stacking AD587s for higher output voltage? (20V, 30V, etc.)

[TimNJ]

Hello,

when doing PWM the linearity does not come for free.

- you already mentioned the rise and fall times
- then there is different resistance of the switch when switching the reference or GND
- switch leakage currents
- charge injection from the PWM input to the output.

of course most of them are also temperature dependant.

there is a EDN-cirquit which combines 2 16-bit PWM signals to a 32 Bit PWM output with a fast settling filter.

https://www.edn.com/design/other/4326640/DC-accurate-32-bit-DAC-achieves-32-bit-resolution
do not believe all values claimed for the ciruit. I guess it is calculated only theoretically without having built a real cirquit.

some measurements with the famous EDN 32-bit PWM-DAC and different switches attached:
with jelly bean CD4051 I get 120 ppm non linearity. (0.6 mV max)
 (the y-scale is error in mV for a 5V input, the x-scale is the PWM-value (0-65535) applied simultaneous to both pwm signals)

after much trimming and using MAX4051A you can get 3-4 ppm linearity with that cirquit.

with best regards

Andreas

Thanks Andreas. I'm not exactly sure I understand how this circuit works. My initial assessment is that the period/phase of the two PWM signals are locked together. Is the on-state value of PT1 1/(2^16) the amplitude of PT0? Then PT1 acts as a fine adjustment, aka controls the least significant 16 bits?

If so, sounds like a pretty good idea, though I feel like there may be some practical roadblocks (that I'm not quite aware of, yet).

I had a similar thought about using two parallel PWMs and then summing them with an op-amp, but having one input scaled down 1/(2^n)...where n is the number of bits you want to add on? (I haven't confirmed that's true yet, fyi). Basically, I could use two 16-bit PWMs with 12-bit overlap to get 16+4-bit = 20-bits. Using a 10V source, my minimum step size would be around 20uV (i think). I suppose offset drift of an op-amp can be trimmed, and as long as you use a low-drift op-amp, accuracy should be reasonable?

Spit-balling once again...

Thanks!

[Kleinstein]

The EDN circuit uses a kind of synchronous filter to get fast settling, despite the relatively low PWM frequency. The synchronous filter can add extra errors from charge injection, which depends on the voltage level or voltage dependent on resistance. So it is kind of elegant, but not so well suited for super higher accuracy.
The more normal way would be a higher order filter - slower, but more predictable. Besides the normal filter function there can be settling due to DA in the capacitors. So settling to the very last ppm will take quite some time. There are chances for a speed-up, but here it starts to get really tricky.

How the main and fine PWM are combined in the EDN circuit is also a little unusual: they add a little to the reference and ground level. The simpler ways and maybe better would be having a second larger resistor for the smaller part, combining at the input of the filter. Having 0.1 % resistors in the combing circuit would limit the extra accuracy too about 8-9 Bits unless an adjustment is done.

Some overlap (thus fine PWM equal to maybe 2-4  LSB steps could be useful for checking the scaling, but more could be more like a problem as it would need more accurate scaling and fine PWM drivers.
So it would be more like 16 Bit coarse PWM, 2 Bits overlap and 16 Bits fine PWM. Thus a theoretical resolution of up to 30 Bits, with some lost in rounding for adjusting the fine scale in software and a lower accuracy than resolution. Even if not absolute linear, the DNL can still be quite good, as PWM is usually (nearly by definition) monotonic.

I would take a look at the circuit for the Fluke 5700 series calibrators. They include a reasonable easy way of compensating for the difference in switch resistance. One could build a similar circuit with modern CMOS switches (e.g. DG4xx) at some places. It still takes a few critical parts: 1 very linear resistor (thus usually low TC and not very small size). A few good caps with low leakage and low DA to keep residual settling times short. A good layout might be needed to avoid RF noise / spikes to cause funny / hard to predict effects. Also parasitic capacitance around the resistor can be a problem. Super fast switching is not the best way as it causes more RF trouble. There is a small range at the bottom and near full scale that is problematic anyway. The good range is more like 1% to 99%.

[Andreas]

yes PT0 is the most significant word
and PT1 are the LSB bits.

Both PWM signals are mixed (not summed as mentioned in the article) by the 15.6 R and (1Meg + 9200R).
So the maximum output voltage is 65535/65536 * VREF when both PWM-values are 0xFFFF
I had lowest output ripple when PT2 is not a 50% PWM but near 0xF800 or 97%.

LTC1151 are chopper amplifiers with very low offset. (no adjustment needed).

I would also make some overlap since 15.6 Ohms * 65536 will never give exactly 1.0092 Meg.
You could use 51 Ohms 0.1% resistors to get nearly 2 bits overlap.

The 3 integration capacitors around the LTC1151 should be Polypropylene type.

with best regards

Andreas

[TimNJ]

The EDN circuit uses a kind of synchronous filter to get fast settling, despite the relatively low PWM frequency. The synchronous filter can add extra errors from charge injection, which depends on the voltage level or voltage dependent on resistance. So it is kind of elegant, but not so well suited for super higher accuracy.
The more normal way would be a higher order filter - slower, but more predictable. Besides the normal filter function there can be settling due to DA in the capacitors. So settling to the very last ppm will take quite some time. There are chances for a speed-up, but here it starts to get really tricky.

How the main and fine PWM are combined in the EDN circuit is also a little unusual: they add a little to the reference and ground level. The simpler ways and maybe better would be having a second larger resistor for the smaller part, combining at the input of the filter. Having 0.1 % resistors in the combing circuit would limit the extra accuracy too about 8-9 Bits unless an adjustment is done.

Some overlap (thus fine PWM equal to maybe 2-4  LSB steps could be useful for checking the scaling, but more could be more like a problem as it would need more accurate scaling and fine PWM drivers.
So it would be more like 16 Bit coarse PWM, 2 Bits overlap and 16 Bits fine PWM. Thus a theoretical resolution of up to 30 Bits, with some lost in rounding for adjusting the fine scale in software and a lower accuracy than resolution. Even if not absolute linear, the DNL can still be quite good, as PWM is usually (nearly by definition) monotonic.

I would take a look at the circuit for the Fluke 5700 series calibrators. They include a reasonable easy way of compensating for the difference in switch resistance. One could build a similar circuit with modern CMOS switches (e.g. DG4xx) at some places. It still takes a few critical parts: 1 very linear resistor (thus usually low TC and not very small size). A few good caps with low leakage and low DA to keep residual settling times short. A good layout might be needed to avoid RF noise / spikes to cause funny / hard to predict effects. Also parasitic capacitance around the resistor can be a problem. Super fast switching is not the best way as it causes more RF trouble. There is a small range at the bottom and near full scale that is problematic anyway. The good range is more like 1% to 99%.

Thank you. Perhaps I'm using the term 'overlap' incorrectly. I suppose I really just want two ranges, one for coarse adjustment, and one to sprinkle in a few extra 10s of uV to get better accuracy. I'll have to do a little analysis to see approximately how much fine adjustment I'd need.

I will probably stay away from any fancy filter designs to start. I will probably begin prototyping something soon and will use the simplest approach first, and then build off that.

For those playing along at home, attached is the block diagram for the Fluke 5700 calibrator from the thread previously linked.

yes PT0 is the most significant word
and PT1 are the LSB bits.

Both PWM signals are mixed (not summed as mentioned in the article) by the 15.6 R and (1Meg + 9200R).
So the maximum output voltage is 65535/65536 * VREF when both PWM-values are 0xFFFF
I had lowest output ripple when PT2 is not a 50% PWM but near 0xF800 or 97%.

LTC1151 are chopper amplifiers with very low offset. (no adjustment needed).

I would also make some overlap since 15.6 Ohms * 65536 will never give exactly 1.0092 Meg.
You could use 51 Ohms 0.1% resistors to get nearly 2 bits overlap.

The 3 integration capacitors around the LTC1151 should be Polypropylene type.

with best regards

Andreas

Thanks again. So 'overlap' would ensure that the unit could produce any arbitrary voltage over its range without running into problems? Thank you for clearing up some confusion.

[Jay_Diddy_B]

Hi,

I am very sceptical about EDN design as published, because as other have pointed out it relies on the second channel (the fine channel) having the precise ratio to blend with the first channel (fine) to produce a longer scale length. The idea also relies on the linearity of the coarse channel.

This is somewhat similar to the techniques described in Linear Technique AN-86 combining two DACs, but the EDN lacks the ADC to discipline the DAC.

I would consider an updated version of AN-86 replacing the LT2400 with the LTC2500.

Link: http://www.linear.com/product/LTC2500-32

The key features are:

• ±0.5ppm INL (Typ)
  104dB SNR (Typ) at 1Msps
  148dB Dynamic Range (Typ) at 61sps
  Guaranteed 32-Bit No Missing Codes
  Configurable Digital Filter with Synchronization
  Relaxed Anti-Aliasing Filter Requirements
  Dual Output 32-Bit SAR ADC
  32-Bit Digitally Filtered Low Noise Output
  24-Bit Differential + 7-Bit Common Mode 1Msps Output with Overrange Detection
  

I would use this ADC to discipline the DACs.

Would do you think?

Regards,

Jay_Diddy_B

[TimNJ]

Thanks. Still investigating options. If I go the AN-86 route, then the total project will likely be pretty expensive. If I go the MCU/PWM route, it will (likely) be significantly cheaper. Fluke has sort of "proven" than the PWM option is feasible, but the 5700 series is also 20+ years old, so maybe the design is a little antiquated. I'm a little scared of the AN-86 route at the moment because it seems harder (because I know less about it). But, it may very well be worth while.

Thanks for your input.

[Kleinstein]

The DAC+ADC route is easier on the layout. The costs depend on the ADC used: the LTC2400 is very affordable and there is a chance to compensate for some of the nonlinearity: the linearity is due to a square law part and can thus be measured. Andreas has doe quite some measurements with this. The LTC2500 and similar have ad diffenret type of INL, so no simple correction.

One limitation of modern ADC chips is that they are made for low voltages like 5 V or 3 V - so no direct measurement at 10 V, and at the ppm level even a simple divider is not that simple.

For the EDN PWM circuit the scaling of the fine part is the least problem, it is not that critical and can be checked relative to the main PWM. The problematic part is nonlinearity due to the switches(especially resistance matching) and maybe also from the filter circuit that includes an other CMOS switch.

The 5700 circuit looks rather complicated with a lot of JFET/MOS switches used to include a gain of 2 stage. If one leaves out that stage, the buffer part gets considerably easier. Using ready made CMOS switches instead of discrete mosfets und level shifters could also simplify some parts - at least the linearity correction and the fine PWM. The filter section could use smaller caps (and thus higher resistance) if FET based OPs are used. The Datron 4910 uses only 1 µF caps in a similar circuit.

Even with the PWM DAC one might want to have a good ADC (like the 2400) for checks anyway. There are still a few points to observe and thus linearity is guarantied by design. So at least some checks (similar to those to do linearity corrections on the LTC2400) are needed.

[TimNJ]

The DAC+ADC route is easier on the layout. The costs depend on the ADC used: the LTC2400 is very affordable and there is a chance to compensate for some of the nonlinearity: the linearity is due to a square law part and can thus be measured. Andreas has doe quite some measurements with this. The LTC2500 and similar have ad diffenret type of INL, so no simple correction.

One limitation of modern ADC chips is that they are made for low voltages like 5 V or 3 V - so no direct measurement at 10 V, and at the ppm level even a simple divider is not that simple.

For the EDN PWM circuit the scaling of the fine part is the least problem, it is not that critical and can be checked relative to the main PWM. The problematic part is nonlinearity due to the switches(especially resistance matching) and maybe also from the filter circuit that includes an other CMOS switch.

The 5700 circuit looks rather complicated with a lot of JFET/MOS switches used to include a gain of 2 stage. If one leaves out that stage, the buffer part gets considerably easier. Using ready made CMOS switches instead of discrete mosfets und level shifters could also simplify some parts - at least the linearity correction and the fine PWM. The filter section could use smaller caps (and thus higher resistance) if FET based OPs are used. The Datron 4910 uses only 1 µF caps in a similar circuit.

Even with the PWM DAC one might want to have a good ADC (like the 2400) for checks anyway. There are still a few points to observe and thus linearity is guarantied by design. So at least some checks (similar to those to do linearity corrections on the LTC2400) are needed.

Thanks. Genuinely so thankful for all of the great responses. Saves so much time muddling with solutions that probably won't work (as well as I'd like) in the end.

The PWM DAC + ADC combination sounds like a great idea. Sounds like the idea here is to take advantage of the highly linear nature of modern ADCs to increase the linearity/accuracy of a DAC. I guess that would really relax the requirements of the PWM DAC since errors will be fedback to the PWM controller anyway and compensated for. That sounds like a combination that wouldn't be wildly expensive and possibly very good performance. Thanks for your wisdom again.

[Kleinstein]

One big advantage of the PWM DAC version is that it can work with something like 10 V or maybe even 20 V range. The voltage range is mainly limited by the switches (MOSFETs / MOS switches. The linearity correction needs switches for a slightly higher voltage range than the main PWM (like 2 or 1.5 times).
It is attractive to use a relatively high voltage to make filter noise and offsets (e.g. due to leakage) less critical.
The PWM DAC will also likely have a little ripple / noise due to RF spikes. The main frequency should be ideally very low, but parts are never ideal. It still needs a few precision parts:
1) the averaging resistor (needs to be linear, which kind of implies low TC)
2) the buffer as the filter is likely relatively high impedance (like 100 K range)
3) at least he first two caps of the filter (like 1 µF PP type caps, so kind of large)
    - maybe a little smaller if the PWM frequency is chosen a little higher
4) the buffer for the reference, as the PWM stage(s) will act back on the source.

The DAC+ADC route gets more difficult at more than about 5 V, as it would need a precision divider. A divide by 2 might still be easy, but would at least add some scaling error / uncertainty to adjust form time to time. Here using a pure PWM DAC might not be very attractive, as PWM is slow on adjustments. So if at all it would be PWM for the coarse part and a conventional (e.g. 8 or 12 Bit) DAC for the corrections. 16-18 Bits from PWM + an added 8 Bits fine might be still enough. With the ADC for corrections the DAC could be a R2R or similar, made for low noise mainly.

The pure PWM DAC might want an ADC for the low voltage range to check the scaling, but his would not be that critical. With suitable amplification even the µC internal ADC can work.

[TimNJ]

Thank you for your nice outline of a proposed design scheme and the critical parts/circuit blocks. Always amazed at the amount of knowledge (and willingness to share it) on this forum.

I don't think slow settling time (a few seconds max?) would really be a problem. PWM still sounds okay. As you say, it also has the ability to work directly with higher voltages which could make the instrument more versatile in general. My take on what you wrote is: If the fine adjustment was PWM-based, then the it might be difficult for the correction algorithm to converge on the correct value. A DAC, on the other hand, would be able to react more quickly. (Sounds like some control loop stability issues might arise.) On top of that, PWM fine adjustment would produce additional ripple that a DAC would not.

Thanks.

[Kleinstein]

The ripple from PWM fine adjust would not be a problem, as the amplitude is very small, much smaller as the main PWM. They can both use the same filter.  The advantages of using PWM for the fine adjust too are low cost (no extra filter needed) and good linearity - a good DAC for fine adjust can get expensive if more than 10 or 12 Bits are needed. Still 16 + 8 bit resolution can be fine, so not real not for higher resolution find adjust. 

It depends on the ADC used if the faster settling of the fine adjust would be really relevant. The main time constant of the filter would be still in the 10 ms, maybe 100 ms range. So settling times are not that bad for a small step. It is only for a large step that is takes something like 10 time constants to really get settling to sub ppm levels. In addition there can be a small, but even slower component due to dielectric absorption. This can be some 10-100 ppms for a large step, but those 100 ppms of the small fine range would not be such a problem. So for slow use the PWM for the fine adjust can be OK. It would only be if one want's some kind of approximate compensation of the step response with the fine DAC, that the fast real DAC would be a real advantage.

[TimNJ]

Thanks a bunch. I'll update you and everyone else on the progress.

[cellularmitosis]

INtereting, I am surprised at how well behaved the nonlinearity of the 4051-based setup is.  I wonder how good you could get by making a PWM offset calibration table.

[Andreas]

Hello cellularmitosis,

the error curve is nearly a parabolic shape.
So if you have luck you need only 2 parameters to correct for the error.

But I fear they will be additionally temperature dependent as RDS,on with high and low input voltage at the switch will change about a factor 2 for 100 deg C temperature change.

with best regards

Andreas