Stacking AD587s for higher output voltage? (20V, 30V, etc.)

[TimNJ]

Hi everyone,

I've been looking at some voltage reference ICs for a project I've been thinking about. In the REF102 datasheet, one of the application circuits is a stacked array (series arrangement) of REF102s to produce output voltages that are multiples of 10V. I think I prefer the AD587 for long term stability, so I was curious if there would be any reason I couldn't do that with a few AD587s.

On the same token, would the initial error, long term stability, and temperature stability go up by a factor of N, the number of references? At least as an estimate?

Thanks!

Tim

AD587: http://www.analog.com/media/en/technical-documentation/data-sheets/AD587.pdf

[ap]

Statistically, aging drift ratio and tempco go down by a factor of sqrt(N).

[Kleinstein]

Noise will go down as sqrt(N). However aging drift, pressure effect and also much of the tempco (especially the higher order contributions) tend to be very similar between the units. So there will be only a limited advantage from these. However an amplifier to make 20 / 30 V from 10 V can easily have large extra errors, and these can be avoided.

[lars]

Don´t forget the humidity sensitivity of epoxy packages. These will also not cancel each other.

Lars

[TimNJ]

Noise will go down as sqrt(N). However aging drift, pressure effect and also much of the tempco (especially the higher order contributions) tend to be very similar between the units. So there will be only a limited advantage from these. However an amplifier to make 20 / 30 V from 10 V can easily have large extra errors, and these can be avoided.

Thanks a lot. So, because noise is intrinsically random, it would be reduced (statistically)? But the distribution of the other factors might be narrower (and with an offset) so the combined tempco/age drift would likely be similar to just one reference?

Do you have any insight into how a zero-drift op-amp, like an LTC2057, with an amplification of 2x, would compare to two stacked AD587 refs?

Don´t forget the humidity sensitivity of epoxy packages. These will also not cancel each other.

Lars

I think I would use the ceramic package but thank you for that insight.

[Kleinstein]

For an x2 amplifier, usually the OP is not the critical part. The difficult parts are often the resistors - 2 well matched resistors can be more expensive than the OP. An LTC2057 would not cause a significant offset drift - however it might cause trouble from higher frequency spikes. So it might not be the best choice.

Noise of the different refs is uncorrelated and thus ads as power and thus the square root of N law for many refs. The noise some times adds and sometimes subtracts. So the sum of two uncorrelated noise sources is not twice the voltage, but only twice the power and thus sqrt(2) times the voltage.

The other factors like temperature, aging, pressure are likely highly correlated. So here the relative drift will be likely be only a little better, if at all. The TC and so on will be the average value of the separate refs and it is highly likely the TCs and similar coefficients will have the same sign on all the refs. So chances are the errors can not compensate.

[TimNJ]

For an x2 amplifier, usually the OP is not the critical part. The difficult parts are often the resistors - 2 well matched resistors can be more expensive than the OP. An LTC2057 would not cause a significant offset drift - however it might cause trouble from higher frequency spikes. So it might not be the best choice.

Noise of the different refs is uncorrelated and thus ads as power and thus the square root of N law for many refs. The noise some times adds and sometimes subtracts. So the sum of two uncorrelated noise sources is not twice the voltage, but only twice the power and thus sqrt(2) times the voltage.

The other factors like temperature, aging, pressure are likely highly correlated. So here the relative drift will be likely be only a little better, if at all. The TC and so on will be the average value of the separate refs and it is highly likely the TCs and similar coefficients will have the same sign on all the refs. So chances are the errors can not compensate.

Thanks for your detailed explanation.

Ah yes, I suppose the switching noise of the zero-drift amp could be problematic for a high precision/metrology project. Perhaps I could just use a filter? Reduce the bandwidth of the amp but I'm really only trying to amplify DC.

I suppose I could use two very low tempco-resistors (but not necessarily high precision), and then use a small series pot to micro-adjust the output voltage with a calibrated 7-1/2 or 8-1/2 digit meter?

This might be something to investigate empirically on the bench. That is, comparing a chopper/zero-drift amp against a normal op-amp over time/temperature.

[Andreas]

Hello,

this should also work with AD587.
But consider that the AD587 needs more headroom. (at least 3.5V)
So with 3 stacked references you will need at minimum 33.5V.

Further you have references which sink current in the stack. So the load regulation will be worse at least for those references.

Noise will go down as sqrt(N).

Think twice: this is only valid for paralleling the outputs.
In series connection the noise adds with sqrt(N).
So only the relative noise (noise per volt output voltage) will be reduced.

with best regards

Andreas

[TimNJ]

Hello,

this should also work with AD587.
But consider that the AD587 needs more headroom. (at least 3.5V)
So with 3 stacked references you will need at minimum 33.5V.

Further you have references which sink current in the stack. So the load regulation will be worse at least for those references.

Noise will go down as sqrt(N).

Think twice: this is only valid for paralleling the outputs.
In series connection the noise adds with sqrt(N).
So only the relative noise (noise per volt output voltage) will be reduced.

with best regards

Andreas

Thank you!

Is there any reason that an AD587 (or other) feeding a zero-drift op-amp with a gain of 3 (or any value) would not work just as well? Perhaps I'm reading the spec sheets wrong, but noise doesn't seem like it would be a problem. Additionally, an offset incurred by nature of the op-amp should be able to be nulled out with a offset adjustment pot...I think(?) That's all assuming I have a known good meter to calibrate this against.

On that note, I do not have a suitable meter at the current time but am considering a Keithley 2010 with 7-1/2 digits/ 0.0025% (1yr) basic DCV accuracy. It's about the best I can afford. If I calibrate my metrology circuit using a cal'd DMM spec'd at 0.0025%, then is my circuit effectively 0.0025% accurate? Do I also add my worst case ppm drift over time and temperature to that? Let's assume that's (somewhat correct) and the absolute accuracy of my circuit is 0.0035%. If I want to calibrate another meter using my reference circuit, what level of accuracy should the target meter be in comparison to my reference. 1/2, 1/5, 1/10? I've seen Fluke cite 1/5 but not sure where that came from. This is something that has confused me for a while and can't wrap my head around.

Anyway, if anyone could shed some light on those ideas or point me to some literature that would help me understand, I'd really appreciate it. Thank you again for all your help.

[ap]

First of: Yes, sure, square law decrease is all (noise, drift) relative to the output voltage. Otherwise one could build a zero noise voltage ultra high resistor by series connection of many low ohm resistors... Semicondutor drift (special effects such as general drift direction caused e.g. by case stress effects put aside) can be considered as very low frequency noise (noise measurements are therefore sometimes used to predict drift rates; there are some dosc available about this).
Re. combining measurement uncertainties, the GUM is a good guideline:
www.bipm.org/utils/common/documents/jcgm/JCGM_100_2008_E.pdf

[Kleinstein]

Using an amplifier adds errors of the amplifier to the errors of the reference. So the relative error will always be larger than that of the reference. With 2 or 3 references the relative error will be about the same as a single reference, maybe even slightly better.  Noise is better with 3 refs in series than amplifying a reference. It depends on the application if noise is really relevant.

For the amplifier, the modern OPs are usually not a large source of error anymore, but the resistors are still not perfect. These will add to the drift.

Especially with a 30 V reference, it is difficult to measure this directly with a DMM: the usually meters are not very good at 30 V, because they usually start with a divider in this range. Many of the better meters can measure 10 V much better, thus one could measure the 3 source at 10 V and add the numbers to get a considerably better result than a direct 30 V reading.  With most precision meters the specs in the 10 V (or maybe 20 V) range are much better than for the higher (e.g. 100 V) ranges.

[d-smes]

I tried this with AD581's.  I added a load resistor to the bottom stage and set load current slightly higher than the quiescent current such that all stages source current (AD581 can only sink 5 uA).  With two stages it was OK but when I went to many stages, it oscillates.  I then set it up so each reference had R-C decoupling on its +Vs pin.  Still oscillates.  I set it aside for another day.   

[TimNJ]

First of: Yes, sure, square law decrease is all (noise, drift) relative to the output voltage. Otherwise one could build a zero noise voltage ultra high resistor by series connection of many low ohm resistors... Semicondutor drift (special effects such as general drift direction caused e.g. by case stress effects put aside) can be considered as very low frequency noise (noise measurements are therefore sometimes used to predict drift rates; there are some dosc available about this).
Re. combining measurement uncertainties, the GUM is a good guideline:
www.bipm.org/utils/common/documents/jcgm/JCGM_100_2008_E.pdf

Thank you for that valuable link. My thoughts are quite scattered about characterizing a new piece of metrology equipment based off of the stated accuracy of its calibrator.

Using an amplifier adds errors of the amplifier to the errors of the reference. So the relative error will always be larger than that of the reference. With 2 or 3 references the relative error will be about the same as a single reference, maybe even slightly better.  Noise is better with 3 refs in series than amplifying a reference. It depends on the application if noise is really relevant.

For the amplifier, the modern OPs are usually not a large source of error anymore, but the resistors are still not perfect. These will add to the drift.

Especially with a 30 V reference, it is difficult to measure this directly with a DMM: the usually meters are not very good at 30 V, because they usually start with a divider in this range. Many of the better meters can measure 10 V much better, thus one could measure the 3 source at 10 V and add the numbers to get a considerably better result than a direct 30 V reading.  With most precision meters the specs in the 10 V (or maybe 20 V) range are much better than for the higher (e.g. 100 V) ranges.

I suppose I have to come up with an allowable noise figure. I'm trying to calibrate 4-1/2 digit meters (and maybe 5-1/2 meters depending on how this all goes). I'm not exactly sure what is realistic/attainable. Maybe 10-25uVp-p? I have much more reading to do, to figure out what's necessary and how to accurately measure such low noise levels.

The reason I want to be able to get up to ~30V is a handful of older (but still popular meters) want to be calibrated at 19V, 29V, 30V, etc.

I tried this with AD581's.  I added a load resistor to the bottom stage and set load current slightly higher than the quiescent current such that all stages source current (AD581 can only sink 5 uA).  With two stages it was OK but when I went to many stages, it oscillates.  I then set it up so each reference had R-C decoupling on its +Vs pin.  Still oscillates.  I set it aside for another day.   

Thank you for this!! It may be something I will still try just for the sake of experiment, but good to know.

[TimNJ]

For reference, here is the idea I've been toying with. Relays sound like a disaster but with a sufficiently high resistance kevlin-varley divider, perhaps the contact resistance will not be a problem.

[The Soulman]

Nice project! Word of advice from a newb: simpler=better.
A fully automated kvd would be pretty cool but would require not only expensive resistors but also expensive relays (low resistance, low leakage, low thermal EMF) and would be a major pain to verify without a proper high resolution dmm.

Have a look at the calibrator from Ian Johnston: http://www.ianjohnston.com/index.php/videos/20-video-blog-022-handheld-precision-digital-voltage-source#compare
He uses a (highly linear) 18 bit dac, good enough for 4,1/2 digits possible 5,1/2 dmm's.
Not saying you should go and buy one but just have a look at the design.

[Jay_Diddy_B]

Hi group,
You can use LT1236. The performance is slightly different shunt versus source. You can connect the LT1236 in series, but I would drive them with a constant current source. Similar specs to the AD587.



Regards,

Jay_Diddy_B

[TimNJ]

Nice project! Word of advice from a newb: simpler=better.
A fully automated kvd would be pretty cool but would require not only expensive resistors but also expensive relays (low resistance, low leakage, low thermal EMF) and would be a major pain to verify without a proper high resolution dmm.

Have a look at the calibrator from Ian Johnston: http://www.ianjohnston.com/index.php/videos/20-video-blog-022-handheld-precision-digital-voltage-source#compare
He uses a (highly linear) 18 bit dac, good enough for 4,1/2 digits possible 5,1/2 dmm's.
Not saying you should go and buy one but just have a look at the design.

You are definitely right that keeping it simple reduces the possibility of unintended errors being introduced to the system. I think I kind of have a fascination with the KVD more than anything.

Ah, I remember reading about/watching videos about Ian's calibrator. Cool device! I thought about using a DAC, but I guess in my head, I was thinking, "No DAC could possibly match the performance of a voltage reference plus KVD"...but that probably isn't so. Doing device matching on the silicon level probably isn't that hard compared to the macro/discrete equivalent.

That said, with an 18-bit DAC (maybe 16-bits usable?), you can't calibrate ultra-precise meters, but the guaranteed performance of the DAC might be more important than the hypothetical higher resolution of a 6 or 7 decade KVD. i.e. I might be more confident in a fully tested/spec'd DAC (of lower resolution) than my attempt at an automated KVD. That also said, if I could characterize the KVD, and it turned out pretty good, then maybe it'd be worth something...

Before I scratch this idea completely, would there be any application where an automated KVD (like the one I sketched up) would be beneficial/out perform a DAC based device? Probably not.

Thanks for the insight!

[TimNJ]

Hi group,
You can use LT1236. The performance is slightly different shunt versus source. You can connect the LT1236 in series, but I would drive them with a constant current source. Similar specs to the AD587.



Regards,

Jay_Diddy_B

Thank you for that. Excellent to know

[guenthert]

Ah, I remember reading about/watching videos about Ian's calibrator. Cool device! I thought about using a DAC, but I guess in my head, I was thinking, "No DAC could possibly match the performance of a voltage reference plus KVD"

You might want to look at http://cds.linear.com/docs/en/application-note/an86f.pdf as well as a $30k implementation: https://www.eevblog.com/forum/metrology/2000-post-teardown-and-study-of-fluke-5700a-calibrator/ .

[TimNJ]

Ah, I remember reading about/watching videos about Ian's calibrator. Cool device! I thought about using a DAC, but I guess in my head, I was thinking, "No DAC could possibly match the performance of a voltage reference plus KVD"

You might want to look at http://cds.linear.com/docs/en/application-note/an86f.pdf as well as a $30k implementation: https://www.eevblog.com/forum/metrology/2000-post-teardown-and-study-of-fluke-5700a-calibrator/ .

Thanks! AN86 was definitely an inspiration for this project. I was mostly looking at the 2nd half of the document which focused on the "traditional" KVD implementation. (It seemed easier, at first glance. Not so much anymore.) But, looking at the ADC/DAC implementation now, a lot of the pitfalls of the traditional design seem to be erased. Would not need a boatload of relays and precision resistors. This might be a fairly interesting long-term project to get invested in. That is, basically adapting the AN86 design to make a commercially-viable universal calibrator.

Ian did a great job, so perhaps no reason to reinvent the wheel, but a (properly done) AN86-based design might be able to push even higher levels of accuracy and stability. I do wonder, though, if AN86 has existed for over 15 years, why something similar hasn't made it to market. That is, an economical calibrator. Perhaps there is no market for it at all?

AN86 implements the error correction code on a PIC MCU using assembly. Seems like an low-cost FPGA might be a good candidate in 2017. Will have to get a better grasp on the design before I get ahead of myself though.

Side note, there are DACs like the AD5791 which can just about pull off this level of performance, but they are also about $100/ea. That said, $100 might be justifiable for what you get.

[Kleinstein]

To a certain level, the ADC+DAC solution works. However SD-ADCs  are good and maybe better than many DAC chips, there accuracy is limited. Not that much improvement since the old LTC2400.

For generating a precise DC, there are two more options: one going the AC way and use a precision AC transformer and AC/DC converter with switches. This viable and use in the datron 1281 meter for internal calibration. Also some Russian precision DMMs are supposed to use this way.

A second and probably easier method is using precision PWM. The Fluke 5700 and similar calibrators use it. Especially with a µC to generate the PWM signal and modern parts this looks like a viable way for DIY. There seem to be sum Chinese DIY instructions / implementations this way.

There is not that much market for cheap calibrators. An important part for a calibrator is trust in the company. In some cases a cheap supply in combination with a good meter are used - viable for something like 3 or 4 digit meters.

[TimNJ]

To a certain level, the ADC+DAC solution works. However SD-ADCs  are good and maybe better than many DAC chips, there accuracy is limited. Not that much improvement since the old LTC2400.

For generating a precise DC, there are two more options: one going the AC way and use a precision AC transformer and AC/DC converter with switches. This viable and use in the datron 1281 meter for internal calibration. Also some Russian precision DMMs are supposed to use this way.

A second and probably easier method is using precision PWM. The Fluke 5700 and similar calibrators use it. Especially with a µC to generate the PWM signal and modern parts this looks like a viable way for DIY. There seem to be sum Chinese DIY instructions / implementations this way.

There is not that much market for cheap calibrators. An important part for a calibrator is trust in the company. In some cases a cheap supply in combination with a good meter are used - viable for something like 3 or 4 digit meters.

Thanks for your invaluable knowledge, again. So what is the technical advantage of a PWM based solution? Is high linearity easier to achieve? (That's my guess.) Most microcontrollers I've worked with only have 16-bit PWM resolution, but perhaps there are better that I'm not aware of.

Yes, I agree about the market for cheap calibrators. But I also feel that a well documented product with lots of testing/data to back it might be good enough for some people/labs. Maybe not the big players, though.

[Kleinstein]

The PWM way can be used as a slow, but very linear DAC. It takes a little more than just a basic digital output and a filter, but the circuit is still manageable and does not need high stability parts. It still needs at least one very linear resistor though. So there should be very little drift with temperature and age. There are a few limitations very close the the ends of the range as the on or off time get too short for settling.

The usual µC internal PWM is only 16 Bits, but there are a few ways around this. There are a few µCs with special high resolution PWM that might add something like 4 extra bits and a simulated very high base frequency. However much more than 24 Bits as a pure PWM would produce a rather low frequency and is thus not that practical. One can use a kind of dithering / sigma delta like modulation to reduce the low frequency part and thus simplify filtering a little, and only need a lower HW PWM resolution.

Even if the PWM resolution is only lets say 16 Bits, the linearity can be much better. So it is possible to add a second smaller signal and this way get a higher resolution. The scaling of the second signal only needs to as accurate as the added resolution and is thus not that critical. With the scale of the second signal good to 0.1 % one could add about 9-10 Bits of extra resolution. There are ways to check the scaling so that the µC could adjust the numbers if needed with relatively moderate effort - so the scaling factor would not even need to be long time stable.

[TimNJ]

The PWM way can be used as a slow, but very linear DAC. It takes a little more than just a basic digital output and a filter, but the circuit is still manageable and does not need high stability parts. It still needs at least one very linear resistor though. So there should be very little drift with temperature and age. There are a few limitations very close the the ends of the range as the on or off time get too short for settling.

The usual µC internal PWM is only 16 Bits, but there are a few ways around this. There are a few µCs with special high resolution PWM that might add something like 4 extra bits and a simulated very high base frequency. However much more than 24 Bits as a pure PWM would produce a rather low frequency and is thus not that practical. One can use a kind of dithering / sigma delta like modulation to reduce the low frequency part and thus simplify filtering a little, and only need a lower HW PWM resolution.

Even if the PWM resolution is only lets say 16 Bits, the linearity can be much better. So it is possible to add a second smaller signal and this way get a higher resolution. The scaling of the second signal only needs to as accurate as the added resolution and is thus not that critical. With the scale of the second signal good to 0.1 % one could add about 9-10 Bits of extra resolution. There are ways to check the scaling so that the µC could adjust the numbers if needed with relatively moderate effort - so the scaling factor would not even need to be long time stable.

Again, thank you. I see your point. The LTC1599 spec'd in AN86 has a settling time of 2us. For this purpose, that of course, is pretty unnecessary. I think a 1sec settling time would still be quite reasonable. I see TI and Infineon have an extension for some of their uCs called HRPWM (High Resolution PWM).

I'll have to think about what to do with the PWM signal once its generated. Ideally, we want the PWM signal to control a switch that connects the reference voltage (10V, for ex.) to the filter network. Whatever it is, it will need to turn on/off very quickly to avoid rounding off the rising/falling edges. Given that the filter network will be connected to the input of a buffer, the IR drop across the switch will likely be small, but also predictable. Thus, we can trim the reference voltage to get a perfect 10.000V at the start of the filter network.

Just some thoughts.

Thanks again.

[Andreas]

Hello,

when doing PWM the linearity does not come for free.

- you already mentioned the rise and fall times
- then there is different resistance of the switch when switching the reference or GND
- switch leakage currents
- charge injection from the PWM input to the output.

of course most of them are also temperature dependant.

there is a EDN-cirquit which combines 2 16-bit PWM signals to a 32 Bit PWM output with a fast settling filter.

https://www.edn.com/design/other/4326640/DC-accurate-32-bit-DAC-achieves-32-bit-resolution
do not believe all values claimed for the ciruit. I guess it is calculated only theoretically without having built a real cirquit.

some measurements with the famous EDN 32-bit PWM-DAC and different switches attached:
with jelly bean CD4051 I get 120 ppm non linearity. (0.6 mV max)
 (the y-scale is error in mV for a 5V input, the x-scale is the PWM-value (0-65535) applied simultaneous to both pwm signals)

after much trimming and using MAX4051A you can get 3-4 ppm linearity with that cirquit.

with best regards

Andreas

[TimNJ]

Hello,

when doing PWM the linearity does not come for free.

- you already mentioned the rise and fall times
- then there is different resistance of the switch when switching the reference or GND
- switch leakage currents
- charge injection from the PWM input to the output.

of course most of them are also temperature dependant.

there is a EDN-cirquit which combines 2 16-bit PWM signals to a 32 Bit PWM output with a fast settling filter.

https://www.edn.com/design/other/4326640/DC-accurate-32-bit-DAC-achieves-32-bit-resolution
do not believe all values claimed for the ciruit. I guess it is calculated only theoretically without having built a real cirquit.

some measurements with the famous EDN 32-bit PWM-DAC and different switches attached:
with jelly bean CD4051 I get 120 ppm non linearity. (0.6 mV max)
 (the y-scale is error in mV for a 5V input, the x-scale is the PWM-value (0-65535) applied simultaneous to both pwm signals)

after much trimming and using MAX4051A you can get 3-4 ppm linearity with that cirquit.

with best regards

Andreas

Thanks Andreas. I'm not exactly sure I understand how this circuit works. My initial assessment is that the period/phase of the two PWM signals are locked together. Is the on-state value of PT1 1/(2^16) the amplitude of PT0? Then PT1 acts as a fine adjustment, aka controls the least significant 16 bits?

If so, sounds like a pretty good idea, though I feel like there may be some practical roadblocks (that I'm not quite aware of, yet).

I had a similar thought about using two parallel PWMs and then summing them with an op-amp, but having one input scaled down 1/(2^n)...where n is the number of bits you want to add on? (I haven't confirmed that's true yet, fyi). Basically, I could use two 16-bit PWMs with 12-bit overlap to get 16+4-bit = 20-bits. Using a 10V source, my minimum step size would be around 20uV (i think). I suppose offset drift of an op-amp can be trimmed, and as long as you use a low-drift op-amp, accuracy should be reasonable?

Spit-balling once again...

Thanks!

[Kleinstein]

The EDN circuit uses a kind of synchronous filter to get fast settling, despite the relatively low PWM frequency. The synchronous filter can add extra errors from charge injection, which depends on the voltage level or voltage dependent on resistance. So it is kind of elegant, but not so well suited for super higher accuracy.
The more normal way would be a higher order filter - slower, but more predictable. Besides the normal filter function there can be settling due to DA in the capacitors. So settling to the very last ppm will take quite some time. There are chances for a speed-up, but here it starts to get really tricky.

How the main and fine PWM are combined in the EDN circuit is also a little unusual: they add a little to the reference and ground level. The simpler ways and maybe better would be having a second larger resistor for the smaller part, combining at the input of the filter. Having 0.1 % resistors in the combing circuit would limit the extra accuracy too about 8-9 Bits unless an adjustment is done.

Some overlap (thus fine PWM equal to maybe 2-4  LSB steps could be useful for checking the scaling, but more could be more like a problem as it would need more accurate scaling and fine PWM drivers.
So it would be more like 16 Bit coarse PWM, 2 Bits overlap and 16 Bits fine PWM. Thus a theoretical resolution of up to 30 Bits, with some lost in rounding for adjusting the fine scale in software and a lower accuracy than resolution. Even if not absolute linear, the DNL can still be quite good, as PWM is usually (nearly by definition) monotonic.

I would take a look at the circuit for the Fluke 5700 series calibrators. They include a reasonable easy way of compensating for the difference in switch resistance. One could build a similar circuit with modern CMOS switches (e.g. DG4xx) at some places. It still takes a few critical parts: 1 very linear resistor (thus usually low TC and not very small size). A few good caps with low leakage and low DA to keep residual settling times short. A good layout might be needed to avoid RF noise / spikes to cause funny / hard to predict effects. Also parasitic capacitance around the resistor can be a problem. Super fast switching is not the best way as it causes more RF trouble. There is a small range at the bottom and near full scale that is problematic anyway. The good range is more like 1% to 99%.

[Andreas]

yes PT0 is the most significant word
and PT1 are the LSB bits.

Both PWM signals are mixed (not summed as mentioned in the article) by the 15.6 R and (1Meg + 9200R).
So the maximum output voltage is 65535/65536 * VREF when both PWM-values are 0xFFFF
I had lowest output ripple when PT2 is not a 50% PWM but near 0xF800 or 97%.

LTC1151 are chopper amplifiers with very low offset. (no adjustment needed).

I would also make some overlap since 15.6 Ohms * 65536 will never give exactly 1.0092 Meg.
You could use 51 Ohms 0.1% resistors to get nearly 2 bits overlap.

The 3 integration capacitors around the LTC1151 should be Polypropylene type.

with best regards

Andreas

[TimNJ]

The EDN circuit uses a kind of synchronous filter to get fast settling, despite the relatively low PWM frequency. The synchronous filter can add extra errors from charge injection, which depends on the voltage level or voltage dependent on resistance. So it is kind of elegant, but not so well suited for super higher accuracy.
The more normal way would be a higher order filter - slower, but more predictable. Besides the normal filter function there can be settling due to DA in the capacitors. So settling to the very last ppm will take quite some time. There are chances for a speed-up, but here it starts to get really tricky.

How the main and fine PWM are combined in the EDN circuit is also a little unusual: they add a little to the reference and ground level. The simpler ways and maybe better would be having a second larger resistor for the smaller part, combining at the input of the filter. Having 0.1 % resistors in the combing circuit would limit the extra accuracy too about 8-9 Bits unless an adjustment is done.

Some overlap (thus fine PWM equal to maybe 2-4  LSB steps could be useful for checking the scaling, but more could be more like a problem as it would need more accurate scaling and fine PWM drivers.
So it would be more like 16 Bit coarse PWM, 2 Bits overlap and 16 Bits fine PWM. Thus a theoretical resolution of up to 30 Bits, with some lost in rounding for adjusting the fine scale in software and a lower accuracy than resolution. Even if not absolute linear, the DNL can still be quite good, as PWM is usually (nearly by definition) monotonic.

I would take a look at the circuit for the Fluke 5700 series calibrators. They include a reasonable easy way of compensating for the difference in switch resistance. One could build a similar circuit with modern CMOS switches (e.g. DG4xx) at some places. It still takes a few critical parts: 1 very linear resistor (thus usually low TC and not very small size). A few good caps with low leakage and low DA to keep residual settling times short. A good layout might be needed to avoid RF noise / spikes to cause funny / hard to predict effects. Also parasitic capacitance around the resistor can be a problem. Super fast switching is not the best way as it causes more RF trouble. There is a small range at the bottom and near full scale that is problematic anyway. The good range is more like 1% to 99%.

Thank you. Perhaps I'm using the term 'overlap' incorrectly. I suppose I really just want two ranges, one for coarse adjustment, and one to sprinkle in a few extra 10s of uV to get better accuracy. I'll have to do a little analysis to see approximately how much fine adjustment I'd need.

I will probably stay away from any fancy filter designs to start. I will probably begin prototyping something soon and will use the simplest approach first, and then build off that.

For those playing along at home, attached is the block diagram for the Fluke 5700 calibrator from the thread previously linked.

yes PT0 is the most significant word
and PT1 are the LSB bits.

Both PWM signals are mixed (not summed as mentioned in the article) by the 15.6 R and (1Meg + 9200R).
So the maximum output voltage is 65535/65536 * VREF when both PWM-values are 0xFFFF
I had lowest output ripple when PT2 is not a 50% PWM but near 0xF800 or 97%.

LTC1151 are chopper amplifiers with very low offset. (no adjustment needed).

I would also make some overlap since 15.6 Ohms * 65536 will never give exactly 1.0092 Meg.
You could use 51 Ohms 0.1% resistors to get nearly 2 bits overlap.

The 3 integration capacitors around the LTC1151 should be Polypropylene type.

with best regards

Andreas

Thanks again. So 'overlap' would ensure that the unit could produce any arbitrary voltage over its range without running into problems? Thank you for clearing up some confusion.

[Jay_Diddy_B]

Hi,

I am very sceptical about EDN design as published, because as other have pointed out it relies on the second channel (the fine channel) having the precise ratio to blend with the first channel (fine) to produce a longer scale length. The idea also relies on the linearity of the coarse channel.

This is somewhat similar to the techniques described in Linear Technique AN-86 combining two DACs, but the EDN lacks the ADC to discipline the DAC.

I would consider an updated version of AN-86 replacing the LT2400 with the LTC2500.

Link: http://www.linear.com/product/LTC2500-32

The key features are:

• ±0.5ppm INL (Typ)
  104dB SNR (Typ) at 1Msps
  148dB Dynamic Range (Typ) at 61sps
  Guaranteed 32-Bit No Missing Codes
  Configurable Digital Filter with Synchronization
  Relaxed Anti-Aliasing Filter Requirements
  Dual Output 32-Bit SAR ADC
  32-Bit Digitally Filtered Low Noise Output
  24-Bit Differential + 7-Bit Common Mode 1Msps Output with Overrange Detection
  

I would use this ADC to discipline the DACs.

Would do you think?

Regards,

Jay_Diddy_B

[TimNJ]

Thanks. Still investigating options. If I go the AN-86 route, then the total project will likely be pretty expensive. If I go the MCU/PWM route, it will (likely) be significantly cheaper. Fluke has sort of "proven" than the PWM option is feasible, but the 5700 series is also 20+ years old, so maybe the design is a little antiquated. I'm a little scared of the AN-86 route at the moment because it seems harder (because I know less about it). But, it may very well be worth while.

Thanks for your input.

[Kleinstein]

The DAC+ADC route is easier on the layout. The costs depend on the ADC used: the LTC2400 is very affordable and there is a chance to compensate for some of the nonlinearity: the linearity is due to a square law part and can thus be measured. Andreas has doe quite some measurements with this. The LTC2500 and similar have ad diffenret type of INL, so no simple correction.

One limitation of modern ADC chips is that they are made for low voltages like 5 V or 3 V - so no direct measurement at 10 V, and at the ppm level even a simple divider is not that simple.

For the EDN PWM circuit the scaling of the fine part is the least problem, it is not that critical and can be checked relative to the main PWM. The problematic part is nonlinearity due to the switches(especially resistance matching) and maybe also from the filter circuit that includes an other CMOS switch.

The 5700 circuit looks rather complicated with a lot of JFET/MOS switches used to include a gain of 2 stage. If one leaves out that stage, the buffer part gets considerably easier. Using ready made CMOS switches instead of discrete mosfets und level shifters could also simplify some parts - at least the linearity correction and the fine PWM. The filter section could use smaller caps (and thus higher resistance) if FET based OPs are used. The Datron 4910 uses only 1 µF caps in a similar circuit.

Even with the PWM DAC one might want to have a good ADC (like the 2400) for checks anyway. There are still a few points to observe and thus linearity is guarantied by design. So at least some checks (similar to those to do linearity corrections on the LTC2400) are needed.

[TimNJ]

The DAC+ADC route is easier on the layout. The costs depend on the ADC used: the LTC2400 is very affordable and there is a chance to compensate for some of the nonlinearity: the linearity is due to a square law part and can thus be measured. Andreas has doe quite some measurements with this. The LTC2500 and similar have ad diffenret type of INL, so no simple correction.

One limitation of modern ADC chips is that they are made for low voltages like 5 V or 3 V - so no direct measurement at 10 V, and at the ppm level even a simple divider is not that simple.

For the EDN PWM circuit the scaling of the fine part is the least problem, it is not that critical and can be checked relative to the main PWM. The problematic part is nonlinearity due to the switches(especially resistance matching) and maybe also from the filter circuit that includes an other CMOS switch.

The 5700 circuit looks rather complicated with a lot of JFET/MOS switches used to include a gain of 2 stage. If one leaves out that stage, the buffer part gets considerably easier. Using ready made CMOS switches instead of discrete mosfets und level shifters could also simplify some parts - at least the linearity correction and the fine PWM. The filter section could use smaller caps (and thus higher resistance) if FET based OPs are used. The Datron 4910 uses only 1 µF caps in a similar circuit.

Even with the PWM DAC one might want to have a good ADC (like the 2400) for checks anyway. There are still a few points to observe and thus linearity is guarantied by design. So at least some checks (similar to those to do linearity corrections on the LTC2400) are needed.

Thanks. Genuinely so thankful for all of the great responses. Saves so much time muddling with solutions that probably won't work (as well as I'd like) in the end.

The PWM DAC + ADC combination sounds like a great idea. Sounds like the idea here is to take advantage of the highly linear nature of modern ADCs to increase the linearity/accuracy of a DAC. I guess that would really relax the requirements of the PWM DAC since errors will be fedback to the PWM controller anyway and compensated for. That sounds like a combination that wouldn't be wildly expensive and possibly very good performance. Thanks for your wisdom again.

[Kleinstein]

One big advantage of the PWM DAC version is that it can work with something like 10 V or maybe even 20 V range. The voltage range is mainly limited by the switches (MOSFETs / MOS switches. The linearity correction needs switches for a slightly higher voltage range than the main PWM (like 2 or 1.5 times).
It is attractive to use a relatively high voltage to make filter noise and offsets (e.g. due to leakage) less critical.
The PWM DAC will also likely have a little ripple / noise due to RF spikes. The main frequency should be ideally very low, but parts are never ideal. It still needs a few precision parts:
1) the averaging resistor (needs to be linear, which kind of implies low TC)
2) the buffer as the filter is likely relatively high impedance (like 100 K range)
3) at least he first two caps of the filter (like 1 µF PP type caps, so kind of large)
    - maybe a little smaller if the PWM frequency is chosen a little higher
4) the buffer for the reference, as the PWM stage(s) will act back on the source.

The DAC+ADC route gets more difficult at more than about 5 V, as it would need a precision divider. A divide by 2 might still be easy, but would at least add some scaling error / uncertainty to adjust form time to time. Here using a pure PWM DAC might not be very attractive, as PWM is slow on adjustments. So if at all it would be PWM for the coarse part and a conventional (e.g. 8 or 12 Bit) DAC for the corrections. 16-18 Bits from PWM + an added 8 Bits fine might be still enough. With the ADC for corrections the DAC could be a R2R or similar, made for low noise mainly.

The pure PWM DAC might want an ADC for the low voltage range to check the scaling, but his would not be that critical. With suitable amplification even the µC internal ADC can work.

[TimNJ]

Thank you for your nice outline of a proposed design scheme and the critical parts/circuit blocks. Always amazed at the amount of knowledge (and willingness to share it) on this forum.

I don't think slow settling time (a few seconds max?) would really be a problem. PWM still sounds okay. As you say, it also has the ability to work directly with higher voltages which could make the instrument more versatile in general. My take on what you wrote is: If the fine adjustment was PWM-based, then the it might be difficult for the correction algorithm to converge on the correct value. A DAC, on the other hand, would be able to react more quickly. (Sounds like some control loop stability issues might arise.) On top of that, PWM fine adjustment would produce additional ripple that a DAC would not.

Thanks.

[Kleinstein]

The ripple from PWM fine adjust would not be a problem, as the amplitude is very small, much smaller as the main PWM. They can both use the same filter.  The advantages of using PWM for the fine adjust too are low cost (no extra filter needed) and good linearity - a good DAC for fine adjust can get expensive if more than 10 or 12 Bits are needed. Still 16 + 8 bit resolution can be fine, so not real not for higher resolution find adjust. 

It depends on the ADC used if the faster settling of the fine adjust would be really relevant. The main time constant of the filter would be still in the 10 ms, maybe 100 ms range. So settling times are not that bad for a small step. It is only for a large step that is takes something like 10 time constants to really get settling to sub ppm levels. In addition there can be a small, but even slower component due to dielectric absorption. This can be some 10-100 ppms for a large step, but those 100 ppms of the small fine range would not be such a problem. So for slow use the PWM for the fine adjust can be OK. It would only be if one want's some kind of approximate compensation of the step response with the fine DAC, that the fast real DAC would be a real advantage.

[TimNJ]

Thanks a bunch. I'll update you and everyone else on the progress.

[cellularmitosis]

INtereting, I am surprised at how well behaved the nonlinearity of the 4051-based setup is.  I wonder how good you could get by making a PWM offset calibration table.

[Andreas]

Hello cellularmitosis,

the error curve is nearly a parabolic shape.
So if you have luck you need only 2 parameters to correct for the error.

But I fear they will be additionally temperature dependent as RDS,on with high and low input voltage at the switch will change about a factor 2 for 100 deg C temperature change.

with best regards

Andreas