[Verilog] Using non-blocking assignments reduces LE's by half!?

[Sailor]

Whoa there...
I'm running Quartus II 13.1, and my device selection is a Cyclone IV. But my RTL diagram is just like the OPs (see attach), except that the +1 value is represented correctly.
How did you get the carry involved?

P.S. how do you get an attached image to be expanded in the post?
P.P.S. the value of +1 is also incorrectly represented in your diagram - just like in the OP's

[PA0PBZ]

P.S. how do you get an attached image to be expanded in the post?

Expand it, copy the url from properties and paste it between img tags:

[Sailor]

Oh, ok. By an (immediate) edit to your initial post?

[vortexnl]

I'm running it on Quartus II 13.1 (x64) edition. And the FPGA development board is the Altera DE0 (not the nano!)

Edit:

The testing from my original post was indeed done on the Max II CPLD, so that might affect these results.

[PA0PBZ]

Oh, ok. By an (immediate) edit to your initial post?

 

[miguelvp]

Whoa there...
How did you get the carry involved?

I just copied the code to a file named cpld.sv since the OP mentioned System Verilog and that was the RTL that it produced.

My device Cyclone IV EP4CE22F17C6N, maybe Quartus II generates different code for different devices and mine happens to trigger the carry?

I haven't studied much at the lower levels so I don't know how the RTL is derived in much detail.

[Sailor]

Ok, that's interesting. I also just copied the OP's code, but to a verilog (.v) file, not System Verilog. Apart from that, everything's pure vanilla. The SV aspect may explain the bad presentation of the +1 value (you and the OP). Maybe the carry arises from the combination of SV + Cyclone IV, but doesn't appear in SV + CPLD. Somewhere, recently, I saw a reference to looking at a lower level (gate level?) than the RTL representation. I'll have a look at the Q II manuals tonight, but maybe a guru could provide some early pointers to the method?

[amyk]

Not gate-level, LE level:

Also you should be able to use the Chip Planner to look at how the LEs were used, which should show the difference more clearly compared to RTL.

[Sailor]

Thanks for that. I must be going blind