hello
recently i've got one of the displays sold by "dexters_lab" here:
https://www.eevblog.com/forum/buysellwanted/(fs-world)-sharp-lj320u21-electroluminescent-320x240-matrix-displays/i've managed to make some simple verilog code that will drive the display, and draw a basic test pattern:
(sorry about the reflections, the display is like a mirror, i peeled of the touch layer, it was cloudy)
the FPGA is clocked from a 50MHz oscillator.
the code is separated in the following modules:
reset_generator.v
- it gets the main clock and raw reset button
- it generates 2 long reset pulses, positive and negative
pixel_timing.v
- receives reset and main clock
- it generates a sequence of 8 pulses - basically a shift register that loops back at the end
- the pulse rate is 50MHz/8 = 6.25MHz
- the first pulse output is used as an enable signal for horizontal and vertical modules
- the last for outpust are OR'ed to generate the pixel clock
horizontal.v
- receives reset, main clock and enable pulse from the timing generator
- outputs
- out_h_sync : H_SYNC pulse, proper logic level
- out_h_active : 1 in active line area, 0 otherwise
- out_h_line_start : a pulse at the start of the active area, not used
- out_h_reset_pulse : a pulse at the start of a new H_SYNC period
- out_h_index[8:0] : current pixel line index, 0 to 319, valid only when out_h_active is 1
vertical.v
- receives reset, main clock, enable
- receives in_h_sync from out_h_reset_pulse
- outputs:
- out_v_sync : proper level V_SYNC signal
- out_v_active : 1 if the current line is display-able, 0 otherwise
- out_v_start : a pulse of the start of the active screen area
- out_v_index[7:0] : line number, from 0 to 239, valid only when out_v_active is 1
sample_video.v
- simple logic that generates the lines from the picture above
sharp_lj320u21.v
- main block, ties everything together
Compilation report:
Flow Status Successful - Sun Apr 16 18:41:17 2017
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name sharp_lj320u21
Top-level Entity Name sharp_lj320u21
Family Cyclone II
Device EP2C8Q208C8
Timing Models Final
Total logic elements 88 / 8,256 ( 1 % )
Total combinational functions 87 / 8,256 ( 1 % )
Dedicated logic registers 40 / 8,256 ( < 1 % )
Total registers 40
Total pins 9 / 138 ( 7 % )
Total virtual pins 0
Total memory bits 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements 0 / 36 ( 0 % )
Total PLLs 0 / 2 ( 0 % )
( can be clocked up to 230MHz )
feel free to criticize the way i wrote it - i've learned verilog by myself, so any comment is useful.
the final scope will be to make a text based status display for my headless servers.
currently i've got it working with an 8x8 font - i will make another thread when i populate the font ROM and i can show a demo.
maybe add a Z80 so i can connect the servers via serial lines and format the data.