6502 memory decoding sanity check?

[BulletMagnet83]

Hi all.

A long time ago I asked about building an SBC. College is done (for now) so I have a bit more time to work on things other than work!

I found this: http://wilsonminesco.com/6502primer/addr_decoding.html which was a great starting point, read some datasheets as best I could, and I ended up with the attached schematic.

Here's what it's MEANT to do:

Select RAM in the range 0000-7FFF
Select I/O bank in the range 8000-BFFF
Select ROM in the range C000-FFFF

My question is: have I missed a trick with PHI2 or the R/W line? I couldn't quite make sense of why the /OE lines on the linked-to page are where they are, as it seems you're only meant to pull them low when you want to do a READ, not select the device. But I may just be being dense 

I don't expect spoonfeeding but if I've cocked up, a little prod in the right direction would be great

[Andy Watson]

I think you need more qualification of the address select - probably with phi2. Your present logic takes care of selecting the appropriate chip when the address lines are stable - you have to consider how those address lines behave in between stable addresses - i.e. as they change they could go through several address regions for which your logic will generate a chip selecting glitch. Pull up the data sheet for the 6502 - in it you should find specifications for when the address (and data) lines are stable - these will probably be referenced to a particular edge of phi2.

[BulletMagnet83]

Thanks Andy, I'm reviewing the timing diagram on WDC's datasheet now. Though I always find them quite difficult to read! From what I can see, while PHI2 is HIGH, No transition is indicated on A0-A15.

(Right now I'm trying to spot the obvious thing I must've missed... there's always at least one!)

Is it worth breadboarding something quick and dirty with something like an 8-bit latch and some LEDs, just to see if it behaves itself before I go any deeper?

[edavid]

I think you need more qualification of the address select - probably with phi2. Your present logic takes care of selecting the appropriate chip when the address lines are stable - you have to consider how those address lines behave in between stable addresses - i.e. as they change they could go through several address regions for which your logic will generate a chip selecting glitch. Pull up the data sheet for the 6502 - in it you should find specifications for when the address (and data) lines are stable - these will probably be referenced to a particular edge of phi2.

1. OP is already qualifying RAM access w/phi2
2. For EPROM, it doesn't matter
3. If you look at his source, that person was only using 6522s and 6551s for I/O, and they have a phi2 input; we don't know if the OP is contemplating using other than 65XX ICs for I/O

[edavid]

I couldn't quite make sense of why the /OE lines on the linked-to page are where they are, as it seems you're only meant to pull them low when you want to do a READ, not select the device.

He wants to get valid data from the RAM and ROM as soon as possible, so he makes sure OE is active as soon as possible.  It's qualified by CS/CE inside the device, so there's no chance of bus contention.

[BulletMagnet83]

1. OP is already qualifying RAM access w/phi2
2. For EPROM, it doesn't matter
3. If you look at his source, that person was only using 6522s and 6551s for I/O, and they have a phi2 input; we don't know if the OP is contemplating using other than 65XX ICs for I/O

One 65C51 and a pair of 65C22s is the plan, eventually! Once I get stage 1 working. Thanks for the explanation on the CS/CE lines, makes sense now!

[banedon]

I used something similar to that decoding scheme in my first 6502 build. The R/W qualification with PHI2 is to ensure that the address and data lines have settled and the previously accessed device has released both buses - this avoids bus contention. 65C22 and 65C51 devices take this in to account themslves and so don't  need to be qualified with PHI2.

With regard to the /OE lines: I think the circuit will set up all attached ICs as if they're going to be accessed (which includes R/W and /OE lines), but only select the chip that is decoded using /CE. I think the /CE input on the chip changes faster than the other inputs as well so it does make sense to do this to get the selected chip to respond faster - the setup is already in place.

I've included an attachment with the decoding that I used and the RAM IC - as you can see, the RAM is the only device which is qualified with PHI2 (CLK in my diagram). The VIA (65C22) doesn't need it as it takes into account the need to act on PHI2 going high, the ROM is slow and the contents cannot be corrupted as well. This leaves the RAM (normally much faster than ROM and can be corrupted if the busses aren't completely set up).

I hope this helps.

P.S. please note that the decoding scheme came from Garth Wilson's primer as well (see http://wilsonminesco.com/6502primer/potpourri.html), although I'm now moving on to using GALs.

[edited to add more info]