Author Topic: 68HC05 instruction timings  (Read 1195 times)

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Offline MaximumspatiumTopic starter

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68HC05 instruction timings
« on: March 29, 2018, 12:15:32 pm »
Hello crews,

does anyone have a good knowledge of the instruction timings of the legacy 68HC05 MCU family? I'm currently trying to understand a firmware of a legacy 68HC05-based device that uses various kinds of waiting loops implemented in the software. In oder to understand them, I need to know how much time each instruction actually takes.

I own a copy of the Motorola user's manual that specifies instruction timings in cycles. What I don't understand is the duration of the single cycle. My device is clocked with a 32768 Hz watch crystal. But the 68HC05 series apparently uses the so-called "bus cycle" for instruction fetching and execution. Unfortunately, I couldn't find any explanation of these mysterious bus cycles and their duration.

Can someone shed some light on this?
Thanks in advance!
Cheers
Max
 

Offline 0xfede

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Re: 68HC05 instruction timings
« Reply #1 on: March 29, 2018, 04:18:31 pm »
Hello Maximumspatium,

the MC68HC05 has bus speed = Fosc/2 or Fosc/32 (the latter if slow mode bit is set).
You can find this info on the datasheet  @page 54, here is the link:
https://www.nxp.com/docs/en/data-sheet/MC68HC05X16.pdf

Best,
0xfede

EDIT: corrected copy/paste typo in page number
« Last Edit: March 29, 2018, 04:51:19 pm by 0xfede »
Semel in anno licet insanire.
 

Offline westfw

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Re: 68HC05 instruction timings
« Reply #2 on: March 30, 2018, 12:24:02 am »
(agreeing with 0xfede):
Quote
M68HC05 Applications Guide — Rev. 4.0

A high-frequency clock source (typically derived from a crystal
connected to the MCU) is used to control the sequencing of CPU
instructions. Typical MCUs divide the basic crystal frequency by
two or more to arrive at a bus-rate clock. Each memory read or
write takes one bus-rate clock cycle. In the case of the
MC68HC705C8 MCU, a 4-MHz (maximum) crystal oscillator clock is
divided by two to arrive at a 2-MHz (maximum) internal processor
clock. Each substep of an instruction takes one cycle of this
internal processor clock (500 ns). Most instructions take two to
five of these substeps; thus, the CPU is capable of executing
about 500,000 instructions every second.
 


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