Author Topic: 74HC165 clock pulse timing  (Read 2417 times)

0 Members and 1 Guest are viewing this topic.

Offline Dan MoosTopic starter

  • Frequent Contributor
  • **
  • Posts: 357
  • Country: us
74HC165 clock pulse timing
« on: February 27, 2017, 06:07:31 am »
Ok, I'm pretty sure this info is on the datasheet, but I'm not able to interpret it.

Using a 74HC165 shift register with a Atmega1284 running (for now anyway) at 8 mHz.

My math says that's 125 nano seconds a cycle. Assuming writing a bit to a port is a single cycle move, how do I know if the shift register can keep up without a delay between clock pulses?

Bonus question: I believe its the setup and hold times I need to read on the datasheet, but I need help reading this bit I guess.
 

Offline obiwanjacobi

  • Frequent Contributor
  • **
  • Posts: 988
  • Country: nl
  • What's this yippee-yayoh pin you talk about!?
    • Marctronix Blog
Re: 74HC165 clock pulse timing
« Reply #1 on: February 27, 2017, 06:53:08 am »
Page 9 Table 7 Max Freq : +/-50 MHz at 5V/25degC

You should write a simple loop that toggles an output pin on the atmega and measure its frequency. I don't think you will get anywhere near 8MHz - more like 800kHz...

Try it.
Arduino Template Library | Zalt Z80 Computer
Wrong code should not compile!
 

Offline bktemp

  • Super Contributor
  • ***
  • Posts: 1616
  • Country: de
Re: 74HC165 clock pulse timing
« Reply #2 on: February 27, 2017, 07:06:53 am »
I don't think you will get anywhere near 8MHz - more like 800kHz...
When using hardware SPI an AVR can do F_CPU/2. That is 8MHz when using a 16MHz xtal.
In software it is hard to get anywhere above F_CPU/6 even with assembler code optimized for speed.
 

Offline Dan MoosTopic starter

  • Frequent Contributor
  • **
  • Posts: 357
  • Country: us
Re: 74HC165 clock pulse timing
« Reply #3 on: February 27, 2017, 07:20:27 am »
fair enough.

But to get back to my main question, do I need to include any delays when pulsing the CP pin on the shift register
 

Offline bktemp

  • Super Contributor
  • ***
  • Posts: 1616
  • Country: de
Re: 74HC165 clock pulse timing
« Reply #4 on: February 27, 2017, 07:34:06 am »
You don't need any delay. Even at 2V supply voltage for the HC165 the worst case setup time (data must be stable before shift clock edge) is only 60ns. The fastest an AVR can do is 1 clock cycle delay, that is 62.5ns delay for 16MHz.
But, if you have long wires between AVR and shift register without any proper termination, bad grounding, etc., increasing the setup and hold time and reducing the clock speed by adding some delays, can help to improve the reliability of the circuit, because it allows for the ringing/overshoots caused by a transition on one wire to stop before sending the next transition.
« Last Edit: February 27, 2017, 07:38:11 am by bktemp »
 

Online tggzzz

  • Super Contributor
  • ***
  • Posts: 19497
  • Country: gb
  • Numbers, not adjectives
    • Having fun doing more, with less
Re: 74HC165 clock pulse timing
« Reply #5 on: February 27, 2017, 09:14:57 am »
The critical points are likely to be:
  • signal integrity: are the voltages within limits at all times, i.e. monotonic transitions, no overshoot/undershoot. This independent of the clock rate since it is determined by the connections between the two circuits and the signal transitions
  • the setup and hold times, as shown in the shift register's datasheet. If the MCU is bitbanging all signals, then you have complete control; if not then you will have to understand the driving circuit's clocking and propagation delays
  • clock rate: see previous point
  • correct PSU decoupling
There are lies, damned lies, statistics - and ADC/DAC specs.
Glider pilot's aphorism: "there is no substitute for span". Retort: "There is a substitute: skill+imagination. But you can buy span".
Having fun doing more, with less
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf