8$ iCE40 developer board..

[Cerebus]

Dunno. I'll figure it out once mine arrives and I have to, until then this head-cold (Which I have had for over a week, dammit!) means I don't have the energy for the dive into the schematics and data sheet that requires. Speculation I can manage, but proper thinkin' and figurin' is a bit beyond me at the moment.

[aventuri]

actually a programmer SW can indeed provide a seamless operation without re-wiring for programming the FPGA on volatile ram or programming permanently the FLASH, and it's just a matter to "swap" the GPIO configuration for MISO/MOSI on the fly! (and keeping the "other" IC reset or disabled to have its pins HiZ!)

this is how it works for icoprog and  what i'm doing with my iceprogrammer, which borrowed from icoprog the basic skeleton but stripped away the Raspberry GPIO library dependancy, as it's currently tailored for A10/A20 Allwinner SOC.

BTW i'm finishing a new revision that's supposed to have:
* configurable pins on the command line, so you can easily wire the upduino against your SBC as you like..
* tested working very easily by me both on ARM32 ( A10/A20 ) and H5 (when compiled as Aarch64..) SOC, and maybe it works on other Allwinner SOCs too.., because luckily enough the Allwinner guys kept the GPIO memory interface exactly at same position and with the same pin names!

[IuriC]

Ordered one, lets see how long it will take to arrive.

[simmconn]

What I received is a torn envelope. Sent an email to the seller with the picture and asked if I can pay another $7.99 to have one shipped in a box. No reply received after 2 and a half weeks.
Just to let you know that there is risk shipping a rigid board in a first-class mail letter, and the seller is apparently too busy to handle shipping problems like this...

[Rasz]

What I received is a torn envelope. Sent an email to the seller with the picture and asked if I can pay another $7.99 to have one shipped in a box. No reply received after 2 and a half weeks.
Just to let you know that there is risk shipping a rigid board in a first-class mail letter, and the seller is apparently too busy to handle shipping problems like this...

as an European shipping anything without confirmation of delivery sounds insane to me. Additional cost for a letter is whole $0.5, and it comes with insurance.

[chickenHeadKnob]

The automated mail handling equipment a letter is subjected to makes sending a small populated board in this way a game of Russian roulette. Mine arrived intact mailed to Canada around 2 weeks after ordering. Both the outside of the  envelope and the board and extra pins revealed signs of rough treatment.   

[martinayotte]

The automated mail handling equipment a letter is subjected to makes sending a small populated board in this way a game of Russian roulette. Mine arrived intact mailed to Canada around 2 weeks after ordering. Both the outside of the  envelope and the board and extra pins revealed signs of rough treatment.

Mines too, but within a week ...

[ale500]

Is it the LED soldered or not ?. I have ordered some too, and the LED was not soldered. I have only seen one with a soldered LED delivered at the end of October.

[asmi]

The automated mail handling equipment a letter is subjected to makes sending a small populated board in this way a game of Russian roulette. Mine arrived intact mailed to Canada around 2 weeks after ordering. Both the outside of the  envelope and the board and extra pins revealed signs of rough treatment.

Yes, header pins arrived all bent with my board too. The board itself seems OK though.

[edavid]

What I received is a torn envelope. Sent an email to the seller with the picture and asked if I can pay another $7.99 to have one shipped in a box. No reply received after 2 and a half weeks.
Just to let you know that there is risk shipping a rigid board in a first-class mail letter, and the seller is apparently too busy to handle shipping problems like this...

as an European shipping anything without confirmation of delivery sounds insane to me. Additional cost for a letter is whole $0.5, and it comes with insurance.

That's because you don't know US shipping rates.  The extra cost for confirmation would be about $1.60 for US addresses and $12 for international mail.  Insurance is more.

simmcomm, just open a PayPal dispute and order another one.

[bingo600]

I've ordered 2 , and both arrived in nice conditions within their envelopes (EU).

/Bingo

[martinayotte]

Is it the LED soldered or not ?. I have ordered some too, and the LED was not soldered.

Mines were having the RGB LED soldered...

[Geoff_S]

Mine came with two 6-pin right-angle headers.  I can't work out what they were meant for.  I'm obviously lacking sufficient intelligence to use this thing 

[dpenev]

Hello,

I've tried latest iceProgrammer on A20 board
./programmer -p is working fine. 

I am getting however as martinayotte got:

./programmer -f < RGB_slow.bin
flash id: 00 c0 80 00 00 02 14 60 00 00 60 00 00 00 00 08 00 00 00 00
writing 101.71kB..
  0% @000000 erasing 64kB sector..
  0% @000000 writing: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  0% @000000 erasing 64kB sector..
  0% @000000 writing: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  0% @000000 erasing 64kB sector..
  0% @000000 writing: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  0% @000000 erasing 64kB sector..

martinayotte did you manage to solve this?
I have CDONE still not connected to the iCE40 module.

EDIT1:
As I saw martinayotte has replaced his flash chip I have decided to give it a try too.
I found M25P40 handy but with it I got:
 
./programmer -f < RGB_slow.bin
flash id: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
writing 101.71kB..
  0% @000000 erasing 64kB sector..
  0% @000000 writing: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  0% @000000 erasing 64kB sector..
  0% @000000 writing: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  0% @000000 erasing 64kB sector..
  0% @000000 writing: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

I have verified that M25P40 has similar command IDs as programmer uses. Hmm strange.

Edit2: I have noticed that flashing with the original flash chip started working if I touch the SS signal.
Experimenting with some pullups pull down seems improve noting. 
I have added some delay in the code as bellow which made flashing a bit more stable at my side but still I get some XXX..
I don't want to investigate now more but it seems we have inexpensive FPGA toy now
....
void spi_begin()
{
    digitalSync(10); //penev
    digitalWrite(SUNXI_ICE_CS, LOW);
    digitalSync(10); //penev
    // fprintf(stderr, "SPI_BEGIN\n");
}

void spi_end()
{
    digitalSync(10); //penev
    digitalWrite(SUNXI_ICE_CS, HIGH);
    digitalSync(10); //penev
    // fprintf(stderr, "SPI_END\n");
}   
...

Best Regards
Dimitar

[martinayotte]

Edit2: I have noticed that flashing with the original flash chip started working if I touch the SS signal.

Yes, I've seen this symptom too, but didn't investigate further since touching is a good workaround ...

[SiliconWizard]

I'd be interested to see how the iCE40 UltraPlus really compares to the MachXO2-ZE.

Of course, the iCE40 is cheaper and has SPRAM.
I'd like to see the real power draw and LUTs usage of a similar design on both devices though, like an LCMXO2-2000ZE vs. iCE40 UP3K for instance. Static current on both is similar (80 µA vs. 75 µA).

[ale500]

I'd like to see the real power draw and LUTs usage of a similar design on both devices though, like an LCMXO2-2000ZE vs. iCE40 UP3K for instance. Static current on both is similar (80 µA vs. 75 µA).

Me too.

I have a design with some 25 % of a 7000ZE with the internal oscillator running at 2.08 MHz (133.3 divided to 2.08), it eats 7 mA when running. The same design didn't seem to report anything useful using my multimeter. I replaced the original 1.2V reg with a MCP1700-1.2, those should be pretty low in quiescent  current.

Did someone do some reliable measurements ?

[iMo]

Mind this UPduino board is intended for very basic demonstration purposes only (blinking the LEDs), not for high performance designs (a poor pcb layout, weak decoupling, no PLL decoupling).

Running J1a forth cpu (~2600LUTs, 15kB bram) at 30MHz (an external Xtal oscillator) takes 19.5-21mA (the current consumption of the UPduino board - do subtract the quiescent currents of the 2x 1117 voltage regulators and SPI flash to get the Ice40UP5k only).

No fun with PLL yet 

[Cerebus]

...no PLL decoupling...

Every third party iCE40 development board that I have seen the schematic for gets this wrong. The damning thing is that right there in the original data sheets they tell you how to do it properly. It's in the document "iCE40 Hardware Check List" under the heading "Analog Power Supply Filter for PLL". It's trivial to get right, but it seems reading data sheets properly is beyond most people.

[iMo]

The trick is the ice40UP5k in SG48 packages does not possess the GNDPLL pin. The appnote says the PLL's decoupling filter shall be wired between VCCPLL and GNDPLL, and "GNDPLL must not be connected to the board's ground". They want to minimize the noise getting into the PLL, therefore in other packages the special GNDPLL pin is directly connected to the internal sensitive PLL circuitry..
As the SG48 got only a single GND at its thermal pad the pcb designers are in doubt where to wire the decoupling capacitors, it seems..

[iMo]

This is a quick workaround (missing VCCPLL decoupling) - I've soldered an 1uF ceramic in between VCCPLL and GND pads.
Not fully according to the appnote recommendation, however, but better than nothing..
Provided as-is, use at your own risk..

[PartialDischarge]

Why is it that Lattice FPGAs are (or seem) much less used than altera or xilinx?  Given that Icecube2 or lattice diamond can be used 'free' and seem easy to program are they used only in some small applications?

[iMo]

Why is it that Lattice FPGAs are (or seem) much less used than altera or xilinx?

Market share 2016:
Xilinx 53%
Altera/Intel 36%
Lattice 3% (but with highest Y2Y growth)
Source: https://www.eetimes.com/author.asp?doc_id=1331443

Xilinx makes $$ with the High-End FPGA devices, used in the most demanding apps you may imagine. A development kit (a 20x20cm board) may cost you up to $250000 (1-2 FPGAs on it).. Currently the supported chips are all high pin count BGA packages, not easy to use, very expensive for smaller designs. Not supported chips today but in DIY friendly flatpacks are the Spartan3/6 etc, "cheap" and available, not supported by Vivado, however. Vivado and old ISE is "free". Technologically the most complex and best FPGAs, very good docs, good support on forums as well.

Lattice with iCE40 occupies the Low-Cost, Low-Power, Low-Performance low-end (the other families might be comparable with Altera's midrange). They target today towards wearable, IOT, handheld devices (usually for interfacing/conditioning/preprocessing in Sensors<->MCUs). Popularity grows today as the packages could be still used easily by DIY market/community. Technologically the "simplest" stuff which does exist (ie. that is why the "icestorm" project is so successful). Designs on Lattice (especially on the iCE40) are usually 2-3x slower, and require 2-3x more fpga resources than the same verilog on today's Xilinxes. Similar tools as the Xilinx, rather basic support. Any pointer to a Lattice forum where we may discuss the stuff??

[daveshah]

I'm currently developing icestorm for this FPGA. At the moment it has experimental, but working, for almost all the features. This will probably be declared stable in the next week or two, except for hard I2C and SPI which are included but will remain experimental for a while.

General icestorm info: http://www.clifford.at/icestorm/
Quickstart demo project (fading RGB) : https://github.com/cliffordwolf/icestorm/tree/master/examples/up5k_rgb
Bigger demo project (NES) : https://github.com/daveshah1/up5k-demos/tree/master/nes
Technical info on UltraPlus features : http://www.clifford.at/icestorm/ultraplus.html

Currently work is in progress on a new development board using this FPGA, that will be a bit more expensive than the upduino but will be properly designed and have many more features, the "icebreaker".

[asmi]

These chips are finally in stock at Digikey (and coming soon at Mouser)! Grab some while you can!