Okay, here it is. Tabs spaces are being a bit silly...
*****************************************
$BASE 10T
PORTA EQU $00
PORTAIE EQU $30B8
PORTAOE EQU $30B0
PORTB EQU $01
PORTBIE EQU $30B9
PORTBOE EQU $30B1
PORTC EQU $02
PORTCIE EQU $30BA
PORTCOE EQU $30B2
PORTD EQU $03
PORTDIE EQU $30BB
PORTDOE EQU $30B3
PORTE EQU $04
PORTEIE EQU $30BC
PORTEOE EQU $30B4
ADC_SC1 EQU $10 ;Status and Control Register 1 page 466
ADC_SC2 EQU $11 ;Status and Control Register 2
ADC_SC3 EQU $12 ;Status and Control Register 3
ADC_SC4 EQU $13 ;Status and Control Register 4
ADC_RH EQU $14 ;Conversion Result High Register
ADC_RL EQU $15 ;Conversion Result Low Register
ADC_CVH EQU $16 ;Compare Value High Register
ADC_CVL EQU $17 ;Compare Value Low Register
ADC_APCTL1 EQU $30AC ;Pin Control 1 Register
ADC_APCTL2 EQU $30AD ;Pin Control 2 Register
WDOG_CS1 EQU $3030 ;Watchdog Control and Status Register 1 page 517
TSC EQU $20 ;page
TCNTH EQU $21 ;page
TCNTL EQU $22 ;page
TMODH EQU $23 ;page
TMODL EQU $24 ;page
TSC0 EQU $25 ;page 277
TCH0H EQU $26 ;page 280
TCH0L EQU $27 ;page 281
TSC1 EQU $28 ;page 277
TCH1H EQU $29 ;page
TCH1L EQU $2A ;page
ACMP EQU $2C ;page 499 analog comparator S/C
;internal clock sources
ICS_C1 EQU $3038 ;ICS Control Register 1 page 191
ICS_C2 EQU $3039 ;ICS Control Register 2 page 192
ICS_C3 EQU $303A ;ICS Control Register 3 page 193
ICS_C4 EQU $303B ;ICS Control Register 4 page 193
ICS_S EQU $303C ;ICS Status Register page 194
ICS_OSCSC EQU $303E ;OSC Status and Control page 195
PMC_SPMSC1 EQU $3040 ;sys pwr management page 52
;VectorStart EQU $FFB0 ;page 56
**********************************
;2048 bytes RAM starts at $0040
EXAMPLE_MSB EQU $40 ;example
********************************************************************************
TRST EQU 4 ;timer reset
TSTOP EQU 5 ;timer stop
TOF EQU 7 ;timer overflow
********************************************************************************
ORG $C000 ; <--- new flash start
START BSET TSTOP,TSC ;stop timer
SEI ;no interrupts
LDA #%00000000
STA WDOG_CS1 ;watchdog timer off, bit 7
;set or clear outputs before changing any DDR bits to 1
MOV #%00000000,PORTA
MOV #%00000000,PORTB ;
MOV #%00000000,PORTD
;DDRs
LDA #%00000000
STA PORTAIE
LDA #%00000000
STA PORTAOE
LDA #%00000000
STA PORTBIE
LDA #%00000000
STA PORTBOE
LDA #%00000000
STA PORTCIE
LDA #%00000000
STA PORTCOE
LDA #%00000000
STA PORTDIE
LDA #%00000001
STA PORTDOE
;LDA #%00000000
;STA PORTEIE
;LDA #%00000000
;STA PORTEOE
LDA #$96 ; = #10010110
STA ICS_OSCSC
LDA #$80 ; = #10000000 BDIV = 0, prescaler = 1
STA ICS_C1
LDA #$00
STA ICS_C2
LDA #$00
STA PMC_SPMSC1
CLC
RSP
CLRX
CLRA
*******************************************************************************
TOP BSET 0,PORTD ;LED on
LDHX #1000 ;1000 = 400uS
TOPLOOP AIX #-1 ;2 8 cyc
CPHX #0 ;3 400nS per loop, 2.5MHz
BNE TOPLOOP ;3 400nS/8 = 50nS per cyc @ 20 meg xtal
; buss = xtal
BCLR 0,PORTD ;LED off
LDHX #1000
BOTLOOP AIX #-1
CPHX #0
BNE BOTLOOP
JMP TOP
*******************************************************************************
ORG $FFFE ;Reset
FDB START
*******************************************************************************