I have never found a good understandable resource for learning Timing constraints - which should remove any need to manually route anything except the most exacting of designs.
I know the words, I understand the concepts, but I just don't get it.
If you find one, let me know.
Mike
The "Timing closure user guide" (UG612) from xilinx is reasonably doable. I'll admit that it is no tutorial, but all the required bits are in it.
Anyways, the main thing is:
- for every clock domain you make a rule (just a 1-liner) that says that all flip-flops in this domain should obey setup/hold requirements for that clock.
- for every dual flip-flop synchronizer between clock domains put a TIMING IGNORE on it, because meta-stability,
weeeey!If you don't have fancier clock domain crossings or multi cycle paths in a pipeline or ddr memory or something, then that's about it really.
As soon as you want anything more, the xilinxness of the software starts to surface. It is soooo easy to make a small mistake in syntax or
a mistake in how you thought you should specify a flip-flop's location in the hierarchy. You thought you correctly specified the target flip-flops that you want to constrain...
No huge error messages, so all is well, right? WRONG! It will gleefully and silently ignore your constraint on that non-existing signal. So now your actual signal
is unconstrained and the place & route is totally free to fsck things up for you.
During the learning curve I've flushed quite a few hours just because of that.
Basically what I am trying to say is this: Assume that EVERY single constraint you specified went horribly wrong. After place& route go over the entire timing report, and check and
double check if you can find
all the signals that you tried to constrain. And after you've done that a few times and get sick of it you write a perl script to check things for you.
Or nowadays that would be a python script.
As for the OP's mention of
"pretty common problems, like for example configurable dynamic routing" ... Mmmh, if you really do mean dynamic reconfiguration, then I would say
that doesn't really qualify as all that common. The number of designs without dynamic reconfiguration far outnumber those with. It's not exactly rocket science, but if you just started
messing with FPGA's I'd steer clear of dynamic reconfiguration for the first few projects.
But if you insist, just google "xilinx dynamic reconfiguration" or "xilinx partial reconfiguration" to check if
that indeed is what you want to use.
And I fully agree with nctnico's comment (minus a small typo). Just write Verilog and let the synthesizer deal with it.