Author Topic: Aldec Active-HDL  (Read 5569 times)

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Offline TNbTopic starter

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Aldec Active-HDL
« on: February 20, 2014, 02:15:14 pm »
Hi! I recently discovered Aldec Active-HDL development environment, it seems quite good and usable, but I just wonder why does it exists in the first place? I mean, does anybody use it in the industry? Because usually I see vendor-specific environments like Quartus II, Xilinx ISE or Actel one. Is there any reason why somebody will use this Active-HDL instead of Quartus II + Modelsim?
 

Offline Stonent

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Re: Aldec Active-HDL
« Reply #1 on: February 21, 2014, 04:48:55 pm »
I hadn't heard of them but since I'm not an engineer, that would play a big part in it.  I read some things on their site and the wikipedia article http://en.wikipedia.org/wiki/Aldec

It looks like they tend to focus on making it easier to transition from FPGAs to custom ASICs. Also it looks like they have some integration with Altium. 
The larger the government, the smaller the citizen.
 

Offline miguelvp

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Re: Aldec Active-HDL
« Reply #2 on: February 24, 2014, 07:42:20 am »
Going through the Quartus II training I've noticed that you can use Active-HDL as a replacement simulation among others. Quartus II comes with an altera edition of modelsim but you can go under Assignments/Settings/EDA Tool Settings and change the simulation to use Active-HDL (default tool is set to none)

You can override the the synthesis as well as other aspects of the flow. On the Altera training they even said that you might want to use third party tools that will obtain better results.

So Altera gives you tools but if someone makes a better tool then why not let you use them (of course you might need to pay way more for those tool chains)

While looking at the configuration settings, I also noticed that there is a "custom" entry, so if you have a way to do it better (I would imagine big company kind of situation) you could have a team developing those tools specifically for their needs.

 

Offline leafi

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Re: Aldec Active-HDL
« Reply #3 on: April 01, 2014, 11:31:26 pm »
They are simply a competitor to ModelSim. I personally like Active HDL just not enough to pay the money to buy it. Lattice uses it as it's simulator. I used it on a XO2 project I had. I learned it in school and found I preferred it to ModelSim just because it was more or a GUI rather than command line. My lead was a modelsim guy but he was very much into command line processing.
 

Offline Tabs

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Re: Aldec Active-HDL
« Reply #4 on: April 14, 2014, 01:06:05 am »
If I remember correctly,

Both Altera and Xilinx are able to use Aldec as their simulator instead of modelsim etc. I hear the Aldec simulator is much faster.
Aldec is also used to create DO-254 and 178B (I think) certifiable systems for aerospace/avionics.

I'm not sure how the performance compares to Xilinx' new Vivado suite which was redeveloped from the ground up.

There's a free student version of it available for download which is valid for 12 months, after which you just renew the student licence for another 12 months. You don't have to be a student to download the student version.

If your new to FPGAs check out digilentinc https://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,729&Cat=14

Their books on digital design were written with their own FPGA boards in mind. The books teach using the student edition of Aldec.
Just get the right language (VHDL/Verilog) as there are versions of the book for both languages and using the graphical design methods to learn FPGAs (also using Aldec).
 

Offline Bassman59

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Re: Aldec Active-HDL
« Reply #5 on: April 14, 2014, 11:53:05 pm »
Hi! I recently discovered Aldec Active-HDL development environment, it seems quite good and usable, but I just wonder why does it exists in the first place? I mean, does anybody use it in the industry? Because usually I see vendor-specific environments like Quartus II, Xilinx ISE or Actel one. Is there any reason why somebody will use this Active-HDL instead of Quartus II + Modelsim?

I use Active-HDL daily.

It should be noted that it is a simulation and verification tool only. It does not do synthesis nor does it do the place-and-route required to get a bitstream. For synthesis you can choose the FPGA vendor-provided tools or you can spend large $$$ to get Mentor Precision or Synopsys Synplify. For place-and-route you need the vendor tools.

The reason some engineers may not have heard of it is because the FPGA vendors provide either a castrated version of Mentor's ModelSim or in the case of Xilinx' ISim their own HDL simulator. In many cases, especially for smaller designs, these tools are more than adequate.

If your designs exceed what the free simulators can do, then you start looking for better alternatives, and there really are only two: Active-HDL and ModelSim. ModelSim is the more expensive of the two, and neither are affordable by the hobbyist. But if you do full-time FPGA development and you have proper test benches with models of external devices (memories, converters, whatever) then you soon realize that the free simulators won't work and the money spent on the Active-HDL or ModelSim license is worthwhile.

 


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