Altera Dual Port RAM bytes shifting error

[muralidhar]

Hi Guys,

I've written a program in VHDL to access CIS and get data and transfer the data over USB using cypress USB transceiver CY7C68013A.

CIS : 1728 Pixels/Line, Output in three parts of 576 bytes.
CIS clock speed : 6.25Mhz, Max 8 Mhz.

FPGA : Cyclone III-EP3C25Q240C8N.

ADC : AD9200, 1st sample appears on the 5th clock hence first 4 clocks cycles are skipped for every line read.

Am using altera Dual Port RAM to get datas from the three outputs simultaneously and storing the datas in to 3 DPRAMs once this operation is done then I read the datas from DPRAM sequentially 1, 2, 3 and write the datas into cypress USB transceiver.

Problem:
When the image is created in the GUI, last four bytes (573,74,75,76) of the output is shifted to the first four bytes(1, 2, 3, 4). This four byte shift happens in all the three outputs.

I couldn't figure out what is the problem in my code.

Please Help. Thanks in advance.

[ale500]

And what does the simulation say ?
I'd be interested to look a bit closer to the relationship between the write clock and pll clock. Could you post a signal trace of the simulator ?

[Scrts]

Hook up SignalTap to see what's actually happening there.

[muralidhar]

thanks. let me run the simulation and use the SignalTap as well to analyse and get back to you.

[muralidhar]

solved.. read data four extra cycles and skipped data first four cycles during write to usb.