Altera Max10 FPGAs

[mikeselectricstuff]

Just found some leaked info on the parallax forums
http://forums.parallax.com/showthread.php/157556-Altera-MAX-10-early-info?p=1295164

Onboard flash, and some (unspecified) analogue functionality

Good that the whole range is available in QFP, but only one option and 0.4mm pitch. 

Are we ever going to see decent FPGAs in mid-pinout QFP/QFNs so they can be used on 2 layer PCBs? 

[mrflibble]

Oh, nice find!

Lets just attach it here as well, in case it goes *poof* on the parallax forum.

Good that the whole range is available in QFP, but only one option and 0.4mm pitch. 

Are we ever going to see decent FPGAs in mid-pinout QFP/QFNs so they can be used on 2 layer PCBs? 

I suspect that that 144-pin QFP is going to be the closest you're going to get from Altera. But you could probably do this thing on 2 layers as well, maybe sacrifice some IO if required.

At any rate, this looks interesting. Lets hope that $30 eval board they mention is going to have good availability.

[marshallh]

I have access to the full datasheet you can ask questions and I'll try to answer them. There are up to 2 ADCs (12bit sar, 1MSPS) with about 14 muxed analog inputs. You can change muxing at runtime to probe signals in succession.

It's basically a Cyclone IV but more focused, and with more onboard toys.

My best guess is we're about 1.5 years off from general availability. Altera takes their time pushing out new silicon.
And the smallest package is 144 eqfp, not likely to have any lower pin count. They are also in very small chipscale and QFN.
I wouldn't hold my breath on competitive pricing, not for a few years. The lattice XO2s are going to continue to be the cheapest thing around.

[marshallh]

San Jose, Calif., September 30, 2014 – Altera Corporation (Nasdaq: ALTR) today announced the availability of non-volatile MAX® 10 FPGAs, Altera’s latest addition to its Generation 10 portfolio. Using TSMC’s 55 nm embedded flash process technology, MAX 10 FPGAs revolutionize non-volatile FPGAs by delivering dual-configuration flash, analog and embedded processing capabilities in a small-form-factor, low-cost, instant-on programmable logic device. MAX 10 FPGAs are shipping today and are supported by a broad collection of design solutions that accelerate system development, including Quartus® II software, evaluation kits, design examples, design services through the Altera Design Services Network (DSN), documentation and training. More information can be found at www.altera.com/max10_pr.

8K LE silicon is now available in low quantities. (I think it is leftover ES silicon from the partner program in August)
Pricewise it is similar to the Cyclone series.
Eval kit:

http://www.mouser.com/ProductDetail/Altera/EK-10M08E144ES-P/?qs=%2fha2pyFadug5SGINdZNV3MsMlTgI0l7zEuXLhyljE15EaIvj3kP77Q%3d%3d

Other eval kits are forthcoming.

Full literature:
http://www.altera.com/literature/lit-max-10.jsp

[miguelvp]

Nice, here is Arrows offering at $30 and with built in programmer and more goodies than the other board, but no stock yet, and their edge connector that is expensive, but I have an adaptor for it already:

http://parts.arrow.com/item/detail/arrow-development-tools/bemicromax10



Edit fixed embedded image and added description:

Board Highlights

Features Altera MAX® 10 FPGA with 8,000 Logic Elements, ADC block, temperature sense diode, onchip-RAM, user flash memory and non-volatile self-configuration.
Extensible via 2 Digital PMOD Interface headers
Allows for further expansion from two 40-pin prototyping headers

One MAX® 10 FPGA (10M08DAF484C8G)
 8,000 LEs
414 Kbit (Kb) M9K memory
256 Kbit (Kb) user flash memory
2 phase locked loops (PLLs)
24 18x18-bit multipliers
1 ADC block – 1 MSa/sec, 12-bit, 18-channels
17 analog inputs
1 temperature sense diode
250 general purpose input/output (GPIO)
Non-volatile self-configuration with dual-boot support

Clocking circuitry

50 MHz oscillator
24 MHz oscillator

External peripherals

8MB SDRAM (4Mb x 16) (ISSI IS42S16400)
Accelerometer, 3-Axis, SPI interface (Analog Devices ADXL362)
DAC, 12-bit, SPI interface (Analog Devices AD5681)
Temperature sensor, I2C interface (Analog Devices ADT7420)

Thermal resistor
Photo resistor

General user input / output

8 user LEDs
2 user Pushbuttons

Prototyping

Two 6-pin PMOD expansion headers
Two 40-pin prototyping headers which provide access to 64 digital I/O
6 analog inputs
One 80-pin BeMicro card edge connector

[mikeselectricstuff]

Mouser have a few parts in stock, with others due Jan 2015

[EEVblog]

Are we ever going to see decent FPGAs in mid-pinout QFP/QFNs so they can be used on 2 layer PCBs? 

I've been asking the "big two" for 15 years now, and the answer has always been no.

[chickenHeadKnob]

Are we ever going to see decent FPGAs in mid-pinout QFP/QFNs so they can be used on 2 layer PCBs? 

I've been asking the "big two" for 15 years now, and the answer has always been no.

I have been looking at the fpga line-ups of lattice xillinx and altera for a micro 'companion' part that is available in a QFP. That also has sufficient I/O's left over after a dual port memory  interface to a beagle-bone GPMC (general purpose memory channel) parallel bus.

 So far the largest QFP I can find is a Cyclone III EPC3C16Q240. 240 pins with 160 I/O's and around $29.10 single quantity; is this the champion for I/O  or is anyone aware of something better?

[Precipice]

I've been asking the "big two" for 15 years now, and the answer has always been no.

Could / should someone keen invent the 'abomination' package, with a chipscale FPGA, configuration EEPROM if needed, handful of tiny switchers for the rails, decouplers as needed, all on a tight-rules multilayer PCB, like you get on BGAs, then bond it out onto a leadframe from
http://www.shinko.co.jp/english/product/leadframe/  (or others, that was first search hit)
Give it a big belly pad for easy grounding and thermals, and off you go, lots of FPGA, some IO.
I've been looking for an excuse to buy a wire bonder (got the die bonder already, impulse purchase...), but I still think this probably isn't it. Surely the market for supercheap Chinese FPGA breakout PCBs with DIP pins is the logical entry to this game, and if you want it smaller, just suck it up and fit BGA. Plough through I/O balls with voltage rails if you must - wastes pins, but makes a board routable on fewer layers.

Of course, anyone going down this path successfully will have their market yoinked away by the FPGA vendors or knockoff shops in about 8 seconds.

[chickenHeadKnob]

Could / should someone keen invent the 'abomination' package, with a chipscale FPGA, configuration EEPROM if needed, handful of tiny switchers for the rails, decouplers as needed, all on a tight-rules multilayer PCB, like you get on BGAs, then bond it out onto a leadframe from
http://www.shinko.co.jp/english/product/leadframe/  (or others, that was first search hit)
Give it a big belly pad for easy grounding and thermals, and off you go, lots of FPGA, some IO.

I have much more modest requirements, don't need special packaging just a simple tested breakout board. HuMandata.jp which advertises on Dave's blog site makes just what I am looking for:http://www2.hdl.co.jp/en/index.php/altera-series1/cycloneiv/acm-204-ql.html

But at $266.00 for the smallest and climbing to the stratisphere I start looking hard at the terasic SoCKIT board.

[mikeselectricstuff]

There are quite a few "module" boards with FPGA+config, regs and often RAM.
But of course everyone's needs are different.
All I want is them to take the die they use in the smaller BGAs and bond it into a 48 or 64 QFP or QFN with 0.5mm pitch. Single supply is nice, if only because it makes it  a lot easier to route on 2 layers with a star or ring under the chip on the top layer.
Internal config mem is nice, but as serial flash is so cheap now , external isn't a big deal.
 Dual supply is sometimes doable on 2L, but depends a lot on pin locations, and limits space for other routing under the chip.

[Bassman59]

I have been looking at the fpga line-ups of lattice xillinx and altera for a micro 'companion' part that is available in a QFP. That also has sufficient I/O's left over after a dual port memory  interface to a beagle-bone GPMC (general purpose memory channel) parallel bus.

 So far the largest QFP I can find is a Cyclone III EPC3C16Q240. 240 pins with 160 I/O's and around $29.10 single quantity; is this the champion for I/O  or is anyone aware of something better?

I don't know how many I/Os you actually need, but what about Xilinx Spartan 3AN XC3S50AN? 144-pin TQFP.

[marshallh]

240pin qfp is basically the biggest they bother with QFP these days. Any bigger and the package parasitics are too big. (Older devices used to be in 300+pin qfps but they also had much slower i/o)

[mikeselectricstuff]

QFPs greater than 144 pins are just silly.

[JoeN]

Good that the whole range is available in QFP, but only one option and 0.4mm pitch. 

I have found that 0.4mm is not significantly harder to hand-solder than 0.5mm.  Have you?

[chickenHeadKnob]

I have been looking at the fpga line-ups of lattice xillinx and altera for a micro 'companion' part that is available in a QFP. That also has sufficient I/O's left over after a dual port memory  interface to a beagle-bone GPMC (general purpose memory channel) parallel bus.

 So far the largest QFP I can find is a Cyclone III EPC3C16Q240. 240 pins with 160 I/O's and around $29.10 single quantity; is this the champion for I/O  or is anyone aware of something better?

I don't know how many I/Os you actually need, but what about Xilinx Spartan 3AN XC3S50AN? 144-pin TQFP.

Yes that would work and it is nice and cheap too. I also looked at these other qfp-144 devices :

• lattice              MachXO  LCMXO1200C                113 I/O
• lattice              MachXo2         XO2-40                   114
• Xilinx               XC6SL9                                          108
• Altera              cyclone IV EP4CE10/6                    91

Along with the cyclone III they would all be workable, life is good except for the option paralysis! I like the MachX02 for non-volatile config-mem, and  the Xilinx  for cheapness but Marshall + free-electron convinced me Quartus is much better than ISE so I prefer Altera.

Valent_f(x) already make a finished board with a XC6SL9,  the Logi-Bone, that has around 32 or 34 I/O for the user left over after interfacing to the Beagle-bone and SDRAM. Somewhat limited and then I would have to learn ISE. With any choice if you run out of I/O on the first fpga you could always add a second for the slower I/O and string it on a spi port as a kind of escape hatch, but that is a little bit dicky.

I expect the next generation of application ARM's and their Intel competitors to ubiquitously offer a single lane GEN 1 PCIe. It is beginning to happen now with Freescale i.Mx6 and intel edison galileo/quark parts and hopefully the fpga's with PCIe hard-block and Xcvrs will be cheaper. And those devices are only going to come in BGA's.

I didn't want to thread high-jack it's just that the MAX 10  intended market niche would appear to be these types of applications.

[mikeselectricstuff]

Good that the whole range is available in QFP, but only one option and 0.4mm pitch. 

I have found that 0.4mm is not significantly harder to hand-solder than 0.5mm.  Have you?

Not tried, but my pick & place, gets a bit marginal at 0.5mm so 0.4 may push it over the edge.
Apart from wasted board space, one of my main issues is that If I need to use a 144 pin package for a design that only needs a couple of dozen pins, I still have the risk of more rework to fix shorted (unnecessary) pins.
OK you can in principle ignore shorts between unused pins but keeping track of which pins matter would be a pain, unless you could arrange for them all to be on one or two sides.

Example on a new project I just started looking at - it would be marginal on a 32 bit MCU but really easy on an FPGA (driving a matrix display from a fast serial bus):
I need 10 I/O pins and about 2K of dual port RAM (1 write, 1 read).
I know Lattice XO2 well so will use that, but the lowest-end part is a 100 pin QFP. 
A 48QFP, or even a QFN32 version of the XO2640 would be perfect.

[Someone]

Are we ever going to see decent FPGAs in mid-pinout QFP/QFNs so they can be used on 2 layer PCBs? 

I've been asking the "big two" for 15 years now, and the answer has always been no.

Spartan 3 and 6 parts in QFP work fine on 2 layer boards, and they have always been supported through the free web pack licenses.

These new MAX10 devices will reduce part count nicely on small embedded systems, and the pricing is good so far.

[mikeselectricstuff]

Spartan 3 and 6 parts in QFP work fine on 2 layer boards, and they have always been supported through the free web pack licenses.

Yes but the smallest part is 100 pins, which takes a ton of board space.
There are plenty of applications that need nowhere need this many pins, and would benefit from a smaller, cheaper package with the same die in it.

[autobot]

Example on a new project I just started looking at - it would be marginal on a 32 bit MCU but really easy on an FPGA (driving a matrix display from a fast serial bus):
I need 10 I/O pins and about 2K of dual port RAM (1 write, 1 read).
I know Lattice XO2 well so will use that, but the lowest-end part is a 100 pin QFP. 
A 48QFP, or even a QFN32 version of the XO2640 would be perfect.

Sounds like a good fit for a xmos mcu. 1/2cores should be enough to handle the display , and you'll get a few extra cores left.

[mikeselectricstuff]

Example on a new project I just started looking at - it would be marginal on a 32 bit MCU but really easy on an FPGA (driving a matrix display from a fast serial bus):
I need 10 I/O pins and about 2K of dual port RAM (1 write, 1 read).
I know Lattice XO2 well so will use that, but the lowest-end part is a 100 pin QFP. 
A 48QFP, or even a QFN32 version of the XO2640 would be perfect.

Sounds like a good fit for a xmos mcu. 1/2cores should be enough to handle the display , and you'll get a few extra cores left.

Maybe but I  shouldn't have to  learn a whole new architecture & toolchain and rewrite already-working code just because FPGA makers can't be arsed to offer a decent range of packages.

[Precipice]

Maybe but I  shouldn't have to  learn a whole new architecture & toolchain and rewrite already-working code just because FPGA makers can't be arsed to offer a decent range of packages.

http://www.xilinx.com/applications/aerospace-and-defense/bare-die-program/index.htm

Go on, roll your own (or pay someone with the gear). No idea what the MOQ is - but I was recently surprised to find that TI support prototyping with bare die.
Although it's not good news that Xilinx seem to regard bare die as a military, rather than a consumer, prospect... Maybe other FPGA houses are more amenable?

[ConKbot]

Maybe but I  shouldn't have to  learn a whole new architecture & toolchain and rewrite already-working code just because FPGA makers can't be arsed to offer a decent range of packages.

http://www.xilinx.com/applications/aerospace-and-defense/bare-die-program/index.htm

Go on, roll your own (or pay someone with the gear). No idea what the MOQ is - but I was recently surprised to find that TI support prototyping with bare die.
Although it's not good news that Xilinx seem to regard bare die as a military, rather than a consumer, prospect... Maybe other FPGA houses are more amenable?

FPGAs rarely are a consumer prospect.  They are there, but usually scale of economy makes using ASICs financially preferred in equipment sold in consumer quantities (hundreds of thousands to millions) obviously, a military product doesnt have the push there to save $0.01 on the BOM because the contractor isnt making millions of the items.

[Rigby]

FPGAs rarely are a consumer prospect.

As the prices of FPGAs continue to go down, that's going to change.  They seem to be appearing more and more often in things I take apart, which could indicate a higher usage rate in consumer goods.

FPGA prices are going down all the time.  I don't know about ASICs, so I can't say if the quantity boundary where it becomes cheaper to develop an ASIC instead of using FPGAs is going up or down.  I can say that I see a lot more FPGAs in consumer goods than I used to, which doesn't really mean anything on its own, I guess.

[ConKbot]

Very true, and especially with shorter time to market on items and shorter life cycles, and the nasty habit to send stuff to consumers without fully testing it and having bugs and just fixing it with firmware updates later.