Artix7 fpga board. External oscillator EMCCLK is pulled down post-config.

[cirthix]

Hi,
I have a newly designed+assembled fpga board based on the artix7 fpga.

An external oscillator (64MHz) is connected to the fpga via the EMCCLK pin.  The clock can be used during configuration (SPI flash chip used can handle 80MHz).  Due to constraints of other parts of the design, the external clock is not connected through an SRCC or MRCC pin.  The internal routing is done through generic routing to an MMCM.  This is OK because the frequency is relatively low and the phase relationship of the output of the MMCM and the input pin is not cared about.

Anyway, the problem that I am having is that prior to configuration, the external oscillator is happily running at 64MHz, but once the fpga is configured (currently using JTAG configuration), the EMCCLK pin is pulled low. 

The external oscillator has it's enable pin connected directly to vcc, so it is the fpga itself pulling the clock down.

In the fpga firmware, the EMCCLK pin is declared as an input, so I don't understand why it is pulled down.  Any ideas?

[Someone]

The EMCCLK signal must be instantiated and used in the design providing the I/O standard definition as the EMCCLK is a multi-purpose pin, or the voltage level will be taken from another pin defined in bank 14. Lock the input to the EMCCLK pin location (see UG475, 7 Series FPGAs Packaging and Pinout Product Specification).
....
The configuration begins with the CCLK generated by the FPGA internal oscillator until the bitstream header is read. If the EMCCLK option is enabled then the FPGA switches from the internal oscillator to the clock found on the EMCCLK pin

So if the clock is being correctly set for the configuration when building the bitstream (loading successfully at that clock rate) then you need to look at the design you are loading onto the FPGA and what its doing with the pin. Time to pull up the routed design and manually follow that pin through.

[cirthix]

The EMCCLK signal must be instantiated and used in the design providing the I/O standard definition as the EMCCLK is a multi-purpose pin, or the voltage level will be taken from another pin defined in bank 14. Lock the input to the EMCCLK pin location (see UG475, 7 Series FPGAs Packaging and Pinout Product Specification).
....
The configuration begins with the CCLK generated by the FPGA internal oscillator until the bitstream header is read. If the EMCCLK option is enabled then the FPGA switches from the internal oscillator to the clock found on the EMCCLK pin

So if the clock is being correctly set for the configuration when building the bitstream (loading successfully at that clock rate) then you need to look at the design you are loading onto the FPGA and what its doing with the pin. Time to pull up the routed design and manually follow that pin through.

The clock is ignored during jtag configuration, but your suggestion of looking through the routed design is a good one.  Doing so now.  Thanks for the tip


Edit:
The OBUF block on the IOB33 (X0Y43) for pin M15 which is the EMCCLK pin for the artix7 in 256pin package does not appear to be used in the design.  The pin input connects to the IBUF which then connects to a net called 'clock_input_IBUF" which has only one other connection being the MMCM.  It looks like the implemented design is doing the right thing.

[cirthix]

Solved

This behavior was not caused by an fpga misconfiguration or design fault.  The board was assembled with a nonconnected ball under the ground pin of the 4pin oscilator. 

An explanation: the oscillator was sinking it's power supply current through the oscilator output through the fpga to ground (half of the time), and the impedance of the fpga input was higher once the pin was configured as an input.  Kind of interesting that it worked at all like this.  With the enable tied to the supply voltage, it was effectively operating on only two pins, +2.5v and fpga pin, still making an ok-looking clock signal.