Hi,
I have a newly designed+assembled fpga board based on the artix7 fpga.
An external oscillator (64MHz) is connected to the fpga via the EMCCLK pin. The clock can be used during configuration (SPI flash chip used can handle 80MHz). Due to constraints of other parts of the design, the external clock is not connected through an SRCC or MRCC pin. The internal routing is done through generic routing to an MMCM. This is OK because the frequency is relatively low and the phase relationship of the output of the MMCM and the input pin is not cared about.
Anyway, the problem that I am having is that prior to configuration, the external oscillator is happily running at 64MHz, but once the fpga is configured (currently using JTAG configuration), the EMCCLK pin is pulled low.
The external oscillator has it's enable pin connected directly to vcc, so it is the fpga itself pulling the clock down.
In the fpga firmware, the EMCCLK pin is declared as an input, so I don't understand why it is pulled down. Any ideas?