Author Topic: Atmega 162 External SRAM problem  (Read 1617 times)

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Offline somlioyTopic starter

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Atmega 162 External SRAM problem
« on: November 11, 2018, 06:14:55 pm »
Hello

Got an atmega hooked up to an external 2kB SRAM via parallell lines where data and address lines are multiplexed (shared with an ADC, and OLED display). However I'm having some issues with data inconsistency from the SRAM. The micro is running at 4.9152Mhz.

I moved the heap to the external sram with the linker options; (address decoder enables SRAM from 0x1800 to 0x1FFF)
Code: [Select]
-Wl,--defsym=__heap_start=0x801800,--defsym=__heap_end=0x801fff -Wl,--relax
I tried running a sram-test program checking if any writing faults occures and then reading faults. This test completes without any errors at power up. However if I do a reset failures occures. If I power cycles again, no failures occures. This repeats.

I'm using the SRAM for a oled-display buffer. Space allocated with calloc;
Code: [Select]
uint8_t *oled_buffer;
oled_buffer = calloc(OLED_WIDTH * OLED_HEIGTH/8, sizeof(uint8_t));

External SRAM is initated with:
Code: [Select]
void SRAM_init() {
// External memory
MCUCR |= (1 << SRE); // External memory enable
SFIOR |= (1 << XMM2); // Masking PC7-PC4 for JTAG interface
}

And as before with the sram-test, the OLED renders perfectly after a power cycle, but after a reset artifacts appear on the display, aswell as missing pixels etc. Artifacts happens during regular re-rendering aswell, only the very first drawing after a power cycle is perfect.

Does anyone have any suggestions? Is this noise issues or possible chip issues (chips arent new)?
Is it necessary to have a LP-filter on the ALE-line as well as pull down resistor?

Address latch: http://www.ti.com/lit/ds/sdas048d/sdas048d.pdf
Sram: https://ntnu.blackboard.com/bbcswebdav/pid-442669-dt-content-rid-17211924_1/courses/194_TTK4155_1_2018_H_1/SRAM%20CY7C185.pdf
Atmega 162: https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2513-8-bit-AVR-Microntroller-ATmega162_Datasheet.pdf
 

Offline iMo

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Re: Atmega 162 External SRAM problem
« Reply #1 on: November 12, 2018, 06:50:28 pm »
Is this correct?? Too many nibbles there, imho..
Code: [Select]
__heap_start=0x801800,--defsym=__heap_end=0x801fff
It could be after power up your code for the verifying your external sram will overwrite the address space from 0x0000 to 0x04FF which is reserved for internal memory and upon reset it crashes somehow..
« Last Edit: November 12, 2018, 09:10:31 pm by imo »
 

Offline T3sl4co1l

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Re: Atmega 162 External SRAM problem
« Reply #2 on: November 12, 2018, 11:33:36 pm »
Missing pixels/bytes suggests timing or signal quality issues.

What does your layout look like?

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline somlioyTopic starter

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Re: Atmega 162 External SRAM problem
« Reply #3 on: November 13, 2018, 11:53:41 pm »
Bypass caps are not shown in the schematic. U1 is the µC, U2 is the latch, U3 is the SRAM, ADC and address decoder on the left. ALE-filter not populated atm.
 


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