Attaching a FIFO to a backplane register interface

[nickolas]

Hello All,

I designed a rudimentary back plane that has ~50 parallel pins. Currently, 8 pins are for the address line, 8 pins are for the data lines, 1 pin is for a clock, and 1 pin is for a not Read/Write command.

These pins go into an FPGA where each register compares the address with its own address as a select, and then depending upon not read/write command, inputs or outputs the data. I have tested reading/writing a few registers and it works fine. I am now looking to have read registers where the user can read data from a FIFO. Is there a standard approach to attaching a FIFO as a read register on an interface such as this?

Thanks for you help.

[hamster_nz]

Usually you have an 'output enable' line too.

You need something to tell the FPGA when to drive or release the data bus.

For a FIFO you may need two registers. One to read the status of the FIFO, the other to read the data.

[nickolas]

Yes, eventually, I was going to beef up the protocol, but wanted to stay as simple as I could until I get some preliminary info about the hardware design (ADC samples at 100 MHz, so I wanted to look at some Bode plots of the analog frontend and try to quantify some stuff about it before revising the PCB design). I can add an output enable line quickly now though.

The question really is about how to get data from the FIFO. Should I use the FIFO itself as a register connected in parallel with the other read/read-write registers within the FPGA or should I create a register than gets filled with the most recent result from the FIFO until the next read occurs?

I have a status register currently that just sees if the FIFO is full or empty, but will add more to this later.