I used the Microsemi 8051 core in a commercial design and it was free for that use, as was the M1 core that they offer. (The M1 only works in the M1-specific variants of the parts.) I used the free version of their tools for the implementation.
Alright then. I'd be interested in seeing the exact license terms. Can't find them on the crappy Microsemi website.
And I currently have no Libero install to dig into...
Yeah, their website is, and has always been, a mess. Links rarely work. When I started that project (which was five years ago!) the FAE assured us that the core was free for our use.
But see
here. The 8051 cores (there are two) are listed under "DirectCore," and it says "
most DirectCores are available free within the Libero tool suite." Click "Processors."
You'll see the two 8051 cores, Core8051 and Core8051s. The former has an "Evaluation" link. The latter does not. This means that you have to buy and license Core8051 for your use. I have not looked into that any further. The Core8051s is available for you to use in any design and there's no other licensing or fees required.
Open Libero SoC and create or open a project. The Core8051s is available in the IP Catalog tab of the Libero screen. It has a green key icon next to the name, indicating that it's fully licensed for you to use. Core8051 is not even listed, unless you download it and add it to the catalog.
There are differences between the two. The Core8051 is much closer to the classic 8051 -- it has the same interrupt structure, timers, UART and I/O ports. The Core8051s dispenses with the peripherals and I/O ports and instead has an APB interface through which you can add your own peripherals. It also has only two interrupts.
This means that if you have code for an existing 8051 design which relies on the original peripherals, you have to use (and pay for) the Core8051. If you're starting from scratch, you can use the Core8051s and roll your own peripherals, so for example you can use an SPI master (or five, if you like) or any wacky thing you like. You just add an APB interface to it, and accessing the APB is done by declaring things to be in XDATA space. The interrupt thing is handled by building your own interrupt controller.
The Core8051s requires an external memory for program storage, so I used a parallel flash device. Their SoftConsole IDE (based on Eclipse, of course) uses sdcc for the compiler and can also program the processor's flash as well as debug, both over JTAG from the FlashPro.