Clock divider /2, Gal22v10B and wincupl

[lk]

Greetings,
Im tinkering with a 6502 computer, that i have working but i wanted to see if i could replace the logic ICS with a PLD, which for the most part was not problem(NAND and inverters), however i have 74HC74, that halves the clock of the system, and i simply cannot figure out how to implement some sort of divider or counter, that i can use to reduce the clock, the only tool i have available is wincupl.
I have looked at the examples, but as the features of different parts affect what you can do, i have a hard time figuring out how to crack this nut.

Below is the nonworking code,  i basically dont know what im doing:) as soon i move past very basic logic.

Is it possible to implement a counter/divider that could halve my clock input?

Code: [Select]

Name     test ;
PartNo   00 ;
Date     12/13/2017 ;
Revision 01 ;
Designer Newbie ;
Company  Lasse ;
Assembly None ;
Location  ;
Device    g22v10 ;

/* *************** INPUT PINS *********************/
PIN   1  =  phi2 ;
PIN   2  =  RW ;
PIN   3  =  A14 ;
PIN   4  =  A15 ;
PIN   5  =  RWINVinput;
PIN   15 =  R;
PIN   11 =  S;
                       

/* *************** OUTPUT PINS *********************/

PIN   19  = topaddressactivelow; 
PIN   18  = outputenable;
PIN   17  = writeenable;
PIN   16  = rwinvoutput;
PIN   14  = Q;

rwinvoutput = !RW;
topaddressactivelow = !( A14 & A15);
outputenable = !( phi2 & RW );
writeenable = !( phi2 & RWINVinput);
Q.D = Q.AR;


Here is a picture of the device i want to use, mainly because i have it and it was cheap
https://photos.app.goo.gl/951yMkD2UiyEEvC03

-lasse

[joeqsmith]

Nice!  I used the 22V10 on the 6801 computer that runs the transient generator, just because. 

PALASM is free and will run under DOSBOX as well.  I tried using CUPL when PALASM would no longer run with Windows NT.  I remember finding several bugs in it and eventually pitched it.   I switched to the Lattice tools which work very well but I am not sure if they offer a free version.     

[edavid]

I don't have WinCUPL installed, but I don't know why you are trying to use AR.  Shouldn't it be something like Q.D = !Q ?

[joeqsmith]

I don't have WinCUPL installed, but I don't know why you are trying to use AR.  Shouldn't it be something like Q.D = !Q ?

Looking at my old CUPL projects, I believe you are correct.

CUPL(WM): Universal Compiler for Programmable Logic
Version 4.8a
Copyright (c) 1983, 1996 Logical Devices, Inc.

4MHZ.d  = !4MHZ                               ;

[lk]

Hi joeqsmith and edavid,

I changed
Q.D = !CLK;
However i have no idea how to get that signal to show up on a pin, when i simulate in proteus, i can see that the Q pin starts high, but the slowly drains to gnd.

I have zero idea what im doing

https://photos.app.goo.gl/951yMkD2UiyEEvC03

Code: [Select]

Name     test ;
PartNo   00 ;
Date     12/13/2017 ;
Revision 01 ;
Designer Newbie ;
Company  Lasse ;
Assembly None ;
Location  ;
Device    g22v10 ;

/* *************** INPUT PINS *********************/
PIN   1  =  CLK ;
PIN   2  =  RW ;
PIN   3  =  A14 ;
PIN   4  =  A15 ;
PIN   5  =  RWINVinput;

PIN   11 =  S;
                       

/* *************** OUTPUT PINS *********************/

PIN   19  = topaddressactivelow; 
PIN   18  = outputenable;
PIN   17  = writeenable;
PIN   16  = rwinvoutput;
PIN   14  = Q;
PIN   15 =  CLKOUT;

rwinvoutput = !RW;
topaddressactivelow = !( A14 & A15);
outputenable = !( CLK & RW );
writeenable = !( CLK & RWINVinput);
Q.D = !CLK;


[edavid]

Hi joeqsmith and edavid,

I changed
Q.D = !CLK;

Try:

Q.D = !Q;

[lk]

Thank you , edavid

that worked

-lasse