Author Topic: CLock Gating | DFLL | GCLK on SamD21  (Read 2080 times)

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Offline eddie0x7c3

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CLock Gating | DFLL | GCLK on SamD21
« on: March 30, 2016, 02:35:03 pm »
So if my understanding  is correct from the code below, which i know is excessively modulated but i just wanted to take it one step at a time and understand what i was doing
anyways...

Code: [Select]
void update_freq()
{


init_clock_source();

init_generic_clocks();

init_FDLL48();

init_generick_clock0();



}

void init_clock_source()
{

//enable clock source and configure with start up time , standby , amplitude
//enable pins for use with crystal , enable the crystal , then enable the output
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ENABLE;
SYSCTRL->XOSC32K.reg|= SYSCTRL_XOSC32K_STARTUP(5) | SYSCTRL_XOSC32K_AAMPEN | SYSCTRL_XOSC32K_EN32K | SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_ENABLE ;

while((REG_SYSCTRL_PCLKSR & (SYSCTRL_PCLKSR_XOSC32KRDY)) == 0); // check system clock status register for clock to be ready

}

void init_generic_clocks()
{
//1 division at generator 1
GCLK->GENDIV.reg = GCLK_GENDIV_DIV(1) | GCLK_GENDIV_ID(1);

//enable | 32khz source | genrator 1
GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_ID(1);

//enable | gen 1 | dfll48m
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(1) | GCLK_CLKCTRL_ID_DFLL48;

}

void init_FDLL48 ()
{

//enable dfll
SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE ;
SYSCTRL->DFLLMUL.reg = (SYSCTRL_DFLLMUL_FSTEP(10)) | (SYSCTRL_DFLLMUL_CSTEP(5)) | (SYSCTRL_DFLLMUL_MUL(1465));
SYSCTRL->DFLLCTRL.reg |=  SYSCTRL_DFLLCTRL_MODE;
   
while((REG_SYSCTRL_PCLKSR & (SYSCTRL_PCLKSR_DFLLLCKC)) == 0);

NVMCTRL->CTRLB.reg |= (NVMCTRL_CTRLB_RWS(1));



}

void init_generick_clock0 ()
{
GCLK->GENDIV.reg = GCLK_GENDIV_DIV(1) | GCLK_GENDIV_ID(0) ;
GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(0) ;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN(0) | GCLK_CLKCTRL_CLKEN |  ;



}

my question concerns mainly the last function
and the overall function of the GCLK
1. The "ID" bits in GENDiv and GENCTRL refer to the Clock i am configuring except in CLKCTRL it refers to the final output peripheral , with the exception of DFLL48 to loop back around...
2. In the last function the code does not specify an "output" ID in CLKCTRL ? so generick clock 0 in this case is the one with 48mhz output...? 
3. Does it have to be Generick CLock 0?
4. To apply this 48mhz to a peripheral would i configure a generick clock with generator 0 as the source? or DFll48?
5.and why is the PORT not an option in the ID section for CLKCTRL


Also what does coarse and fine step do to the DFLL?
« Last Edit: March 30, 2016, 02:37:20 pm by eddie0x7c3 »
EE Student: Year 1 | West Palm Beach FL | "“It is not a dream, it is a simple feat of scientific electrical engineering, only expensive — blind, faint-hearted, doubting world! "    -NT
 
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Online ataradov

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Re: CLock Gating | DFLL | GCLK on SamD21
« Reply #1 on: March 30, 2016, 02:51:51 pm »
1. The "ID" bits in GENDiv and GENCTRL refer to the Clock i am configuring except in CLKCTRL it refers to the final output peripheral , with the exception of DFLL48 to loop back around...
The question is not clear. In both cases they refer to GCLK Generator ID (value 0-7). It is basically the same thing as if there were 8 sets of registers (which would be better, IMO).

2. In the last function the code does not specify an "output" ID in CLKCTRL ? so generick clock 0 in this case is the one with 48mhz output...? 
It sure doses. You are making GCLK0 output 48MHz taken from DFLL.

3. Does it have to be Generick CLock 0?
It can be any GCLK you like.

4. To apply this 48mhz to a peripheral would i configure a generick clock with generator 0 as the source? or DFll48?

You do something like this:
Code: [Select]
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(TC0_GCLK_ID) |  GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(0); This enables clock for TC0 (and TC1, since all timers are doubled up).

Basically in a peripheral you specify GCLK1 that you configured previously.

5.and why is the PORT not an option in the ID section for CLKCTRL
Ports are always clocked, I guess, but I'm not sure with what clock. More reading of the DS is required.

Also what does coarse and fine step do to the DFLL?
Coarse is used to get initial lock and then frequency is fine tuned with fine steps.
Alex
 
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Online ataradov

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Re: CLock Gating | DFLL | GCLK on SamD21
« Reply #2 on: March 30, 2016, 02:55:16 pm »
Here is info on the PORT:
Quote
The PORT is fed by two different clocks: a CPU main clock, which allows the CPU to access the PORT through the low-
latency CPU local bus (IOBUS), and an APB clock, which is a divided clock of the CPU main clock and allows the CPU to
access the PORT registers through the high-speed matrix and the AHB/APB bridge.

And the main clock is derived from GCLK 0. So port is always clocked and does not need additional configuration.
Alex
 
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Offline eddie0x7c3

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Re: CLock Gating | DFLL | GCLK on SamD21
« Reply #3 on: March 30, 2016, 03:10:47 pm »
1. The "ID" bits in GENDiv and GENCTRL refer to the Clock i am configuring except in CLKCTRL it refers to the final output peripheral , with the exception of DFLL48 to loop back around...
The question is not clear. In both cases they refer to GCLK Generator ID (value 0-7). It is basically the same thing as if there were 8 sets of registers (which would be better, IMO).

2. In the last function the code does not specify an "output" ID in CLKCTRL ? so generick clock 0 in this case is the one with 48mhz output...? 
It sure doses. You are making GCLK0 output 48MHz taken from DFLL.
But the ID bits in GCLK are not configured in the last function... thats why i say the the ID bits in the other registeres refers to the generator your configuring but in the CLKTRL register ID does NOT refer to the generator your configuring , otherwise why would the not be set in the last function?  I think in the CLKCTRL the GEN bits refer to the generator your configuring and ID refers to where its going to be output. At least thats what it seems like to me , because ID options are all peripherals in CLKCTRL , while in the other registers the ID bit options are all Generators
EE Student: Year 1 | West Palm Beach FL | "“It is not a dream, it is a simple feat of scientific electrical engineering, only expensive — blind, faint-hearted, doubting world! "    -NT
 

Online ataradov

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Re: CLock Gating | DFLL | GCLK on SamD21
« Reply #4 on: March 30, 2016, 03:35:21 pm »
But the ID bits in GCLK are not configured in the last function... thats why i say the the ID bits in the other registeres refers to the generator your configuring but in the CLKTRL register ID does NOT refer to the generator your configuring

In CLKCTRL register ID field is the ID of the peripheral and GEN is the ID of the GCLK you want this peripheral to be clocked from.
Alex
 
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Offline eddie0x7c3

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Re: CLock Gating | DFLL | GCLK on SamD21
« Reply #5 on: March 30, 2016, 03:49:07 pm »
But the ID bits in GCLK are not configured in the last function... thats why i say the the ID bits in the other registeres refers to the generator your configuring but in the CLKTRL register ID does NOT refer to the generator your configuring

In CLKCTRL register ID field is the ID of the peripheral and GEN is the ID of the GCLK you want this peripheral to be clocked from.

Gotcha! and  in the subsequent registers the ID bits refer to this GCLK in the GEN ID bits
EE Student: Year 1 | West Palm Beach FL | "“It is not a dream, it is a simple feat of scientific electrical engineering, only expensive — blind, faint-hearted, doubting world! "    -NT
 

Online ataradov

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Re: CLock Gating | DFLL | GCLK on SamD21
« Reply #6 on: March 30, 2016, 03:53:07 pm »
ID refers to the main thing you are configuring.

In case of GENCTRL and GENDIV you are applying settings to the GCLK itself, so ID there is ID of the GCLK.

In case of CLKTRL you are configuring a peripheral (this register should really be located in each peripheral), so ID refers to a peripheral.


That clock configuration is very confusing at the beginning, but once you figure it out, it is so hard to go back to parts with fixed clocking scheme.
Alex
 
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