ARM Cortex M7 STM3F746: external bus cache problem (solved)

[bktemp]

I am trying to drive a display using 16bit bus connected to STM32F746's FMC.
I did configure the FMC for SDRAM + SRAM (both share the same data and address lines) and write the data directly to the SRAM address where the display is connected to:

Code: [Select]

volatile uint16_t * const lcd_data = (volatile uint16_t*) 0x60000000;
*lcd_data=value;
When sending a single word I can see the FMC_NWE line pulsing once, as expected. But when sending multiple words in a burst it also pulses only once.
It looks like some caching is happening somewhere, so only one write is generated despite multiple writes being requested. If I add a short pause (5us) after each write, I get the correct number of pulses and the display works, but it is much too slow.
I can rule out the data cache, because it is disabed.

Can any ARM expert give me a clue where the caching happens and how to solve this problem?

[nctnico]

There isn't something like a bus arbiter cache in between? This used to be a problem with PCI I/O on x486 PCs as well where you'd needed to do a read after a write to flush the write cache.

[Koen]

I had the same symptoms and adding a delay also did the trick. I've solved it by adding this :

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MPU->RNR = 1;
MPU->RBAR = 0x60000000;
MPU->RASR = 0x1300002d;
MPU->CTRL = ((uint32_t) 0x00000004) | MPU_CTRL_ENABLE_Msk;
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;I don't remember anything about it but you can try it.

[bktemp]

I had the same symptoms and adding a delay also did the trick. I've solved it by adding this :

Code: [Select]

MPU->RNR = 1;
MPU->RBAR = 0x60000000;
MPU->RASR = 0x1300002d;
MPU->CTRL = ((uint32_t) 0x00000004) | MPU_CTRL_ENABLE_Msk;
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;I don't remember anything about it but you can try it.

It works!

The only difference to my init code seems to be the TEX setting:
All examples I could find used TEX level 1 so I used setting 1, but in your code it is set to 0.

A bit more googeling revealed at least a short description (C, B bits set to 00):
TEX = 1: memory area is set to non-cacheable
TEX = 0: memory area is set to strongly ordered
That makes sense. Thanks!