Communication over JTAG?

[hlavac]

Any JTAG experts here?

I have this nice simple cheap CPLD board (MachXO Breakout Board from Lattice) that I'm learning VHDL/Verilog on.
It has a built in USB JTAG programmer using channel A of FT2232H.

One thing I'm missing is some sort of communication with PC.
It is unbelievable that Lattice did not break out the channel B from the FT2232H to the CPLD or at least to some pads

I was thinking I would try to use the JTAG boundary scan commands (namely INTEST) to load some registers.
According to the BSDL file there are bidirectional boundary cells and INTEST is supported.

I was thinking of using some of the unused input pins, posting data and strobe onto it, to be latched.
I believe that INTEST mode will momentarily disconnect all the I/O pins from the internal logic, and I'll have to live with it.
For some crude register loading, it could work, no?

Or is it a silly idea?

[tszaboo]

No, I believe this is the same principle how the "chipscope" works on xilinx. It lets you to "sample internal signals". How you send this data around on your PC is another question, I have no way of knowing that.

[abyrvalg]

Entering INTEST will also freeze any external clock you use, so you'll need to flip some bit in a scan chain to clock your data in.
You can detect an I/O disconnect state (and react to it somehow) using some input pin pulled to 1 externally, but forced to 0 during INTEST (use PRELOAD to load a known value into the chain before INTEST).

[hlavac]

Good point with the clock.
MachXO has an internal ~22ish MHz RC clock, I wonder if it too goes thru a boundary scan cell...

[abyrvalg]

Checked the board's image, there is nice TQFP FT2232H - why don't just solder 3-4 wires to channel B SPI? Will be easier to program and faster.

[hlavac]

My hands are too shaky for soldering onto legs of 0.5mm pitch TQFP64...

[chickenHeadKnob]

@hlavac: To your original idea it is not silly at all, don't know how to make it work though. It just shows how dumb the designers of these eval boards are. The FTDI has 2 8-bit fifos and an extra serial, such a waste.

 If you are designer of one of these eval boards for the love of all that is good make them modular like the LPC eXpresso cards. What I am saying is have a jtag section and target section that are separable with rows of inch header holes and solder bridges you can cut . So that way you end up with a seperate fpga breakout and reuseable jtag boards with all pins accessable and not commited. Doing it this way costs almost nothing extra! when applied at board layout time.

 Another thing if you make an eval board for a family of small fpga's put the LARGEST fpga in there, because obvious. Lattice was putting the 1200 LUT device in earlier versions of this board - stupid

[hlavac]

Lattice was putting the 1200 LUT device in earlier versions of this board - stupid

It was not this board, it was the one for MachXO2. Can't get hold of that one for some reason...

[chickenHeadKnob]

Lattice was putting the 1200 LUT device in earlier versions of this board - stupid

It was not this board, it was the one for MachXO2. Can't get hold of that one for some reason...

 Yes you are right, I confused the two lines. I was looking at the MACHX02 and ice40 very hard a few months back, and concluded the X02 was the better for me but didn't buy the board yet, too many things to do. FPGA's are hella-difficult to figure out for noobs. If I recall correctly some of the ice40 eval boards had parts with no onchip PLL, big trap for me, but I abandoned looking at those.