Any JTAG experts here?
I have this nice simple cheap CPLD board (
MachXO Breakout Board from Lattice) that I'm learning VHDL/Verilog on.
It has a built in USB JTAG programmer using channel A of FT2232H.
One thing I'm missing is some sort of communication with PC.
It is unbelievable that Lattice did not break out the channel B from the FT2232H to the CPLD or at least to some pads
I was thinking I would try to use the JTAG boundary scan commands (namely INTEST) to load some registers.
According to the
BSDL file there are bidirectional boundary cells and INTEST is supported.
I was thinking of using some of the unused input pins, posting data and strobe onto it, to be latched.
I believe that INTEST mode will momentarily disconnect all the I/O pins from the internal logic, and I'll have to live with it.
For some crude register loading, it could work, no?
Or is it a silly idea?