Page 24 tells you the full story. PLLDIV and CPUDIV do what they say on that diagram. I was going to write a detailed explanation here, but I'd just be verbally describing the diagram!
With this chip, it is impossible to derive 1 MHz CPU clock from 16 MHz primary or secondary oscillators (at least, not without ignoring the "(4 MHz Input only)" warning on that one particular PLL there). Unless there's further dividers elsewhere. You can, however, use the internal oscillator with OSCCON<6:4> = 100, having some fun with manipulating the tuning bits.
If you're thinking this seems odd, this seems unusual to me too. The PLL in my ARM dev board is vastly more versatile than this.
You could also use a simple binary counter chip to divide by 16 for you.
EDIT: Just an additional note to clarify: You expressed a frustration that Table 2-3 only showed clocked configuration "for USB". Just to make it absolutely clear, Table 2-3 is an exhaustive list of all possible clock/oscillator configurations, whether you want USB or not (excepting those with input clock frequencies other than 4/8/12/16/20/24/40/48 MHz, for which use of the PLL is banned and you're restricted to the /1, /2, /3 and /4 options set by CPUDIV) (and except internal oscillator options.)