Hi all,
Not sure if this is the right place to ask this, but I am really confusing myself and could use some help
I'm trying to write a verilog testbench. It's basically supposed to be a waveform that represents an AXI stream transaction:
module master_stream_handshake();
reg axis_aresetn;
reg axis_aclk;
reg [7:0] axis_tdata;
reg axis_tready;
reg axis_tvalid;
initial begin
$dumpfile("stream.vcd");
$dumpvars;
axis_aclk = 0;
axis_aresetn = 0;
axis_tdata = 0;
axis_tvalid = 0;
axis_tready = 0;
#3 axis_aresetn = 1;
#4 axis_tvalid = 1;
axis_tready = 1; // set by slave
#2 axis_tdata = 5;
#2 axis_tdata = 6;
#2 axis_tdata = 7;
#2 axis_tdata = 8;
#2 axis_tdata = 9;
#2 axis_tready = 0;
#10 $finish();
end
always begin
#1 axis_aclk = axis_aclk ^ 1;
end
endmodule
I'm simulating it in iverilog and viewing it with GTKWave (clock period is 2 seconds):
The thing I am getting really confused with is the timing of "writes" (for lack of better word). Basically, my question boils down to this: if I had a bunch of ideal rising edge triggered flip-flops connected to "axis_tdata", what would be its state just after the marker (let's say, 9.1 seconds)? Would it be storing the old value (0x00) or would it be storing 0x05?
I thought that in verilog all "reads" of signals were performed before any "writes", so I would have thought that the register would have 0x00 clocked in at the cursor, then 0x05 would be at the next rising edge. However, GTKWave says the value is 0x05
Looking at the specification itself makes a lot more sense, because all of the waves aren't locked to the clock edges:
Can anyone please point me in the right direction?