My solution provides a glitch-free timer. Isn't that what you want?
If you want to do it the more complicated way, reading the timer register and combining it with the overflow count, it's a bit more code, but still not rocket science. After cli(), if the overflow interrupt flag is set and the timer register value is < 128 then add 1 to the overflow value.
I didn't read your code, but based on the description "This is pretty basic. Just disable interrupts while accessing the counter in RAM. The timer still keeps running without any skew getting added" are you sure that it is glitch free?
Right column is RAM_Counter:Timer Counter for a 16 bit counter, left column is the instructions being run....
0000:FFFF disable interrupts
0000:FFFF read timer. Gives xxxx:FFFFF for timer value (the upper half comes from RAM)
--- timer rolls over here ---
0000:0000 read RAM - GIves 0000:FFFF for timer value
0000:0000 check timer's IRQ flag = true
0000:0000 enable interrupts
-- IRQ happens --
0001:0000 IRQ flag is set, so inc reading from RAM (0000:FFFF => 00001:FFFF)
Or how about:
0000:FFFF disable interrupts
0000:0000 read timer. Gives xxxx:FFFF for timer value (the upper half comes from RAM)
0000:0000 read RAM - GIves 0000:FFFF for timer value
--- timer rolls over here ---
0000:0000 check timer's IRQ flag = true
0000:0000 enable interrupts
-- IRQ happens --
0001:0000 IRQ flag is set, so inc reading from RAM (0000:FFFF => 00001:FFFF)
I guess you are now about to suggest that if an IRQ was flagged you look at the value from the h/w timer, and decide if the IRQ was raised before of after the timer was read (based on the high bit).
Why not just keep it simple...
read RAM value into reg1
read H/W timer into reg2
read RAM value into reg3
if reg3 != reg1
clear reg2 to zero
use reg3:reg2 as timer value
You don't even need to disable interrupts...