Cortex-M0 at 14nm node...

[technix]

Here is a bit of rumor I have heard: someone in China made some Cortex-M0 based microcontroller chips on a 14nm node.

That guy made use of TSMC’s hitch hike production service. The submitted design has to be relatively small, as it occupies the edge of a wafer when a bigger chip took the bulk at the center. That guy lucked out when his Cortex-M0 chip took a ride on a 14nm AMD Ryzen wafer.

Rumor has it that guy’s chip can hit gigahertz using its on-chip PLL and an external clock of 25MHz. That chip has 8MB on-chip SRAM and has a 128MB QSPI stacked beneath it.

I wonder what can he achieve with a gigahertz Cortex-M0. Also should you be the guy that lucked out what other peripheral would you put in there.

[coppice]

People will want M0 cores embedded in various larger devices at 14nm, so a test chip has value. A simple M0 MCU at 14nm makes no sense, as it would be so massively pad limited.

[SiliconWizard]

Indeed, unless you can embed huge amounts of memory and a large quantity (read: very large) of peripherals, the die area a Cortex M0 would take on a 14nm node would be very tiny and the number of pads would be very very limited. Like, extremely. 8MB of SRAM is a lot but the die area is probably still pretty limited, thus the number of pads as well.

To get a higher number of pads and still not waste too much die area, one could think of implementing sophisticated and programmable I/O cells for each I/O. A world of possibilities. But still, not cost-effective at all for an MCU.

[technix]

People will want M0 cores embedded in various larger devices at 14nm, so a test chip has value. A simple M0 MCU at 14nm makes no sense, as it would be so massively pad limited.

What would you do if you can create such a chip? Assume you have all the bonding options - COB, stacked die, etc.

One example: a three-die stack: 14nm main die on top, has the gigahertz Cortex-M0 core, 16-20MB SRAM (padding out the space using SRAM since there will be quite a few pads albeit small,) PLL, QSPI master controller, AHB matrix and pads for two AHB ports and QSPI, 40nm QSPI Flash die is placed in the middle, bought from a third party manufacturer; 130nm I/O die on the bottom with AHB/APB bridge, DMA controller, various peripherals, power regulators, logic level shifters etc.

[technix]

Indeed, unless you can embed huge amounts of memory and a large quantity (read: very large) of peripherals, the die area a Cortex M0 would take on a 14nm node would be very tiny and the number of pads would be very very limited. Like, extremely. 8MB of SRAM is a lot but the die area is probably still pretty limited, thus the number of pads as well.

To get a higher number of pads and still not waste too much die area, one could think of implementing sophisticated and programmable I/O cells for each I/O. A world of possibilities. But still, not cost-effective at all for an MCU.

If die space is a concern, how about packing 32 Cortex-M0 cores into there along with 16MB SRAM in 16 1MB blocks, a (very complicated now) 33-slave 19-master AHB matrix, a AHB-APB bridge for the two local peripherals on the 14nm die, a PLL and a QSPI master controller? This should pad out the die enough to have pads for two AHB ports and a QSPI port. This die should be able to be used in a three-die stack along with a QSPI die (as internal Flash) and a 130nm or 65nm I/O die.

[coppice]

Indeed, unless you can embed huge amounts of memory and a large quantity (read: very large) of peripherals, the die area a Cortex M0 would take on a 14nm node would be very tiny and the number of pads would be very very limited. Like, extremely. 8MB of SRAM is a lot but the die area is probably still pretty limited, thus the number of pads as well.

To get a higher number of pads and still not waste too much die area, one could think of implementing sophisticated and programmable I/O cells for each I/O. A world of possibilities. But still, not cost-effective at all for an MCU.

If die space is a concern, how about packing 32 Cortex-M0 cores into there along with 16MB SRAM in 16 1MB blocks, a (very complicated now) 33-slave 19-master AHB matrix, a AHB-APB bridge for the two local peripherals on the 14nm die, a PLL and a QSPI master controller? This should pad out the die enough to have pads for two AHB ports and a QSPI port. This die should be able to be used in a three-die stack along with a QSPI die (as internal Flash) and a 130nm or 65nm I/O die.

Are you just trying to think up the world's weirdest device, or do you have some practical high volume use for this thing?

[ataradov]

I would rather have one CM7 core than 32 CM0 unless you have more efficient communication channel than main SRAM. And even then it sound like hugely unbalanced device.

[NorthGuy]

I think it's lot of possibilities - fast bit-banging, working with fast ADCs, up to 100 MHz perhaps, sheer calculations. If you connect 8 pins to it, it makes wonderful peripheral which can do practically anything. Although fast IO buffers are needed as well.

[brucehoult]

Here is a bit of rumor I have heard: someone in China made some Cortex-M0 based microcontroller chips on a 14nm node.

Sure, no reason why not. Except maybe contractual. As far as I know all commercially available CM0 only go to 50 MHz.

SiFive's E20 is quite similar to a C-M0, although with full 16/32 bit opcode instruction set like the bigger Cortex chips. But the pipeline is similar at only 2 stages. ESilicon is using the E20 as a controller for SerDes for 56G/112G links on 7nm chips.

I don't know what MHz it is achieving there.

[mark03]

Isn't there a fundamental trade-off between static (leakage) power and dynamic power as you go down in feature size?  I don't have the requisite background to understand this, but it seems to be the pattern, e.g., in FPGA families.  Does the same thing hold for an MCU?

If somebody wants to bulk up a fine-geometry Cortex-M core with some kind of filler, I vote for FPGA fabric.  I'd love to see something like a scaled-down Zynq, on both the processor and fabric sides.  Perhaps a fast M4 or M7 core, with FPGA fabric equivalent to the smallest Spartan-7 devices.

[SiliconWizard]

Indeed, unless you can embed huge amounts of memory and a large quantity (read: very large) of peripherals, the die area a Cortex M0 would take on a 14nm node would be very tiny and the number of pads would be very very limited. Like, extremely. 8MB of SRAM is a lot but the die area is probably still pretty limited, thus the number of pads as well.

To get a higher number of pads and still not waste too much die area, one could think of implementing sophisticated and programmable I/O cells for each I/O. A world of possibilities. But still, not cost-effective at all for an MCU.

If die space is a concern, how about packing 32 Cortex-M0 cores into there along with 16MB SRAM in 16 1MB blocks, a (very complicated now) 33-slave 19-master AHB matrix, a AHB-APB bridge for the two local peripherals on the 14nm die, a PLL and a QSPI master controller? This should pad out the die enough to have pads for two AHB ports and a QSPI port. This die should be able to be used in a three-die stack along with a QSPI die (as internal Flash) and a 130nm or 65nm I/O die.

Are you just trying to think up the world's weirdest device, or do you have some practical high volume use for this thing?

As I said, I don't think there would be a market for those weird monsters, that would have to be priced high on top of that.

For those interested in fiddling with ideas like this, there are multiple services that you could use (given that you have enough means, but still a lot less than what you'd need for a dedicated wafer), called MPW. See: https://en.wikipedia.org/wiki/Multi-project_wafer_service

As of yet, I don't know of any that gives access to a 14nm process, but you can get access to a TSMC 40nm process at Europractice for instance, and soon 28nm.

[coppice]

Isn't there a fundamental trade-off between static (leakage) power and dynamic power as you go down in feature size?

The latest and greatest process is usually launched with horrible leakage, and over time they learn ways to tame it. However, the leakage normally remains above the best the next larger geometry has achieved. If you made an small MCU today in 14nm, a lot of people would find its leakage unworkable, unless it is put in a very deep sleep state, where bringing it back is basically a reboot.

[technix]

Indeed, unless you can embed huge amounts of memory and a large quantity (read: very large) of peripherals, the die area a Cortex M0 would take on a 14nm node would be very tiny and the number of pads would be very very limited. Like, extremely. 8MB of SRAM is a lot but the die area is probably still pretty limited, thus the number of pads as well.

To get a higher number of pads and still not waste too much die area, one could think of implementing sophisticated and programmable I/O cells for each I/O. A world of possibilities. But still, not cost-effective at all for an MCU.

If die space is a concern, how about packing 32 Cortex-M0 cores into there along with 16MB SRAM in 16 1MB blocks, a (very complicated now) 33-slave 19-master AHB matrix, a AHB-APB bridge for the two local peripherals on the 14nm die, a PLL and a QSPI master controller? This should pad out the die enough to have pads for two AHB ports and a QSPI port. This die should be able to be used in a three-die stack along with a QSPI die (as internal Flash) and a 130nm or 65nm I/O die.

Are you just trying to think up the world's weirdest device, or do you have some practical high volume use for this thing?

As I said, I don't think there would be a market for those weird monsters, that would have to be priced high on top of that.

For those interested in fiddling with ideas like this, there are multiple services that you could use (given that you have enough means, but still a lot less than what you'd need for a dedicated wafer), called MPW. See: https://en.wikipedia.org/wiki/Multi-project_wafer_service

As of yet, I don't know of any that gives access to a 14nm process, but you can get access to a TSMC 40nm process at Europractice for instance, and soon 28nm.

I think that is a TSMC Shanghai specific service and you need to pull some strings to access that. For that service you are only guaranteed a rough bracket of the process (for example specify 16nm and you will get anywhere between 22nm and 11nm, while specifying 28nm you would get anywhere between 32nm and 22nm) and the actual process you get is determined by whatever high-volume chip is currently running in their production lines. He timed it when AMD Ryzen was in the pipelines, so he got that 14nm process.

[brucehoult]

For those interested in fiddling with ideas like this, there are multiple services that you could use (given that you have enough means, but still a lot less than what you'd need for a dedicated wafer), called MPW. See: https://en.wikipedia.org/wiki/Multi-project_wafer_service

As of yet, I don't know of any that gives access to a 14nm process, but you can get access to a TSMC 40nm process at Europractice for instance, and soon 28nm.

The FU540 SoCs on the HiFive Unleashed boards are all from TSMC 28nm Multi-Project Wafers ("shuttle runs"). The first ones came back from TSMC in January, and there have been several more runs since then.

I think the 28nm service has been available for a few years, that's just the first time we used it.

I believe the chips (with five 1.5 GHz 64 bit cores, each with 32k icache and 32k dcache per processor, and 2 MB shared L2) end up costing several hundred dollars each on MPWs. If mass-produced on dedicated wafers they would be maybe a couple of bucks each -- but then you're stuck with the entire cost of making the masks, so you'd better make a lot of wafers from one set of masks.

[znroot]

IHMO a 14-nm tech node costs too much for the market target of a Cortex-M0, and it make no-sense to use a such advanced FinFET technology to achieve better performances in a low-FET count, low complexity MCU like a Cortex-M0.


If you make a comparison taking into account a more older 45/90/130nm technology node,  the benefits obtained in an advanced FinFET technology are maybe interesting but probably the don't worth the exponential increased production costs.


So, probably, it is only a test chip to make practice for a more advanced project.

[technix]

If a Cotrex-M0 was pointless for 14nm node, will dual or quad gigahertz Cortex-M4F cores on 14nm make any sense?

[ataradov]

If a Cotrex-M0 was pointless for 14nm node, will dual or quad gigahertz Cortex-M4F cores on 14nm make any sense?

It will depends on the overall architecture and peripherals. What memory will they run from at 1 GHz?

In general MCU cores at such high frequencies don't make much sense to me.

And the price is important, of course.

[ali_asadzadeh]

NXP has done some nice M7 (i.MXRT) till 600MHz, I think either NXP or ST or some china guy would definitely do one of these M babies in 14nm. and they would totally make sense

[technix]

If a Cotrex-M0 was pointless for 14nm node, will dual or quad gigahertz Cortex-M4F cores on 14nm make any sense?

It will depends on the overall architecture and peripherals. What memory will they run from at 1 GHz?

In general MCU cores at such high frequencies don't make much sense to me.

And the price is important, of course.

The chip in my head has dual Cortex-M4F or Cortex-M7F and dual Cortex-M0, all of which can run at gigahertz speed, 16MB SRAM for both program and data, as well as a DDR3 controller for bulk RAM. The dual M0 is being used as a replacement DMA controller for the dual M4F/M7F. Initial program loading is done from mask ROM (that sets up QSPI XIP at a lower core clock speed) and then QSPI Flash in XIP mode. For peripherals I see two RGMII or even XGMII interfaces.

That chip, can probably make a good home router chip in my opinion.

[legacy]

Here is a bit of rumor I have heard: someone in China made

who are you? a sort of spy? secret agent? whoever unclassifiable identity with a high-level badge? 



let me quote Elvis Presley when he met Richard Nixon:

can I have my badge?

I want my badge, too 

[legacy]

(O.T., 50 cents of entertainment

the lucky men who own a special badge can access classified information ... such as who shot shortly after noon on November 22, 1963, to President John F. Kennedy when he rode in a motorcade through Dealey Plaza in downtown Dallas, Texas. From which planet in the galaxy did the UFO come from when it in mid-1947 it crashed at a ranch near Roswell? and which kind of technology was found there? What exactly happened to Marilyn Monroe; after years and years of broadcasting, haven't scientists yet received any pong (reply) after we have sent several ping radio-signals to the NuSTAR powerful radio galaxy Cygnus A? (perhaps .. we have been talking to them on the wrong frequency? modulation? or something?); is there any life on the Jupiter's moon Europa, under just 100meter of ice in the liquid water? do they look like fishes? or polyps? Can we fry them and eat with chips?

and ... this question is really interesting since my car drinks too much gas and gas is too much expensive in Europe ... will it be really possible to get free-gas from the Titan planet? or have  USA, China, Russia, anyone already have any plan about putting some fees on it?

this kind of super secret information

but, it's widely known that Elvis loved gold, big glasses, and collecting badges, and he met Nixon to obtain a gold badge, like badges assigned to agents, but just for adding a new item to his collection.

What a ... waste  )

[technix]

Here is a bit of rumor I have heard: someone in China made

who are you? a sort of spy? secret agent? whoever unclassifiable identity with a high-level badge? 



let me quote Elvis Presley when he met Richard Nixon:

can I have my badge?

I want my badge, too 

No I don't have a badge. Someone got the chips and excited and posted a writeup somewhere that allowed me to read an abstract.

[MT]

(O.T., 50 cents of entertainment

Hoorraaay!

the lucky men who own a special badge can access classified information ... such as who shot shortly after noon on November 22, 1963, to President John F. Kennedy when he rode in a motorcade through Dealey Plaza in downtown Dallas, Texas.

The special badge holders and main killers was CIA boss Allen Dulles, FBI boss ,J. Edgar Hoover, Vice president Lyndon B Johnson, each one of them had huge reasons for put an end to JFK. But some more people was also involved such as future to be CIA boss and president Bush etc.

From which planet in the galaxy did the UFO come from when it in mid-1947 it crashed at a ranch near Roswell?
and which kind of technology was found there?

That we dont know yet!

What exactly happened to Marilyn Monroe;

She died.

after years and years of broadcasting, haven't scientists yet received any pong (reply) after we have sent several ping radio-signals to the NuSTAR powerful radio galaxy Cygnus A? (perhaps .. we have been talking to
them on the wrong frequency? modulation? or something?)

Aliens dont broadcast, they know better.

is there any life on the Jupiter's moon Europa, under just 100meter of ice in the liquid water? do they look like fishes? or polyps? Can we fry them and eat with chips?

You are right on all points, i guess!

and ... this question is really interesting since my car drinks too much gas and gas is too much expensive in Europe ... will it be really possible to get free-gas from the Titan planet? or have  USA, China, Russia, anyone already have any plan about putting some fees on it?

No soup for you!

this kind of super secret information

Tell us more?

but, it's widely known that Elvis loved gold, big glasses, and collecting badges, and he met Nixon to obtain a gold badge, like badges assigned to agents, but just for adding a new item to his collection.

Elvis was an Alien!

What a ... waste  )

As always!

[hans]

I would rather have one CM7 core than 32 CM0 unless you have more efficient communication channel than main SRAM. And even then it sound like hugely unbalanced device.

Multi-core systems are indeed harder to program, well up to some degree.
If you can split up your task across multiple cores without task arbitration necessary, it makes finding a dataflow modelling for real-time software analysis so much easier. Having to deal with an online or preemptive RTOS is hell.
A FIFO is an excellent message passing system, as it shifts the whole functional behaviour onto timing aspects only as it eliminates timing from influencing functional behaviour.
Microchip seems to pay attention, as they have implemented it in hardware. Creating a reliable software FIFO is also a relatively easy task, but a bit slower to run.
FIFOs are nice because if you have an upper bound for the read & write speed, with accompanying bursts, it is trivial to find the maximum buffer size you need.

Performing the same kind of modeling on 1 core means you cannot make those upper bounds as tight, resulting in more memory necessary to bridge the introduced jitter of processing.
And in many cases, people don't have a clue and just multiply buffers by a factor of 2 if the software crashes.

[wraper]

For that service you are only guaranteed a rough bracket of the process (for example specify 16nm and you will get anywhere between 22nm and 11nm, while specifying 28nm you would get anywhere between 32nm and 22nm) and the actual process you get is determined by whatever high-volume chip is currently running in their production lines. He timed it when AMD Ryzen was in the pipelines, so he got that 14nm process.

It does not work like this. You must design for particular process from the start.
EDIT: Also it's not like they switch between producing different processes. As 14nm process is running, they make as many chips as they can on this process. They cannot simply switch equipment between making different processes. Not to say they must make as many ICs as they can on the new process to recover costs implementing it as fast as possible before this process becomes obsolete for high price products in a few years. And BTW, Ryzen is currently made by Globalfoundries only. They will use 7nm TSMC for future Ryzen though. TSMC and Ryzen at the same time completely invalidates this rumor.

[wraper]

As of placing additional dies on the corners. It's still extremely expensive because you need additional multi million mask set.

[legacy]

No I don't have a badge. Someone got the chips and excited and posted a writeup somewhere that allowed me to read an abstract.

ah, ok, sort of gossip-man. There is one in every neighborhood.

[legacy]

Multi-core systems are indeed harder to program

like this ?

I had written "interesting", but this one I posted about some time ago is a tri-core and it's too complex, and with "too complex" I mean of the level you need a huge box of pills against your headache 

[technix]

I would rather have one CM7 core than 32 CM0 unless you have more efficient communication channel than main SRAM. And even then it sound like hugely unbalanced device.

Multi-core systems are indeed harder to program, well up to some degree.
If you can split up your task across multiple cores without task arbitration necessary, it makes finding a dataflow modelling for real-time software analysis so much easier. Having to deal with an online or preemptive RTOS is hell.
A FIFO is an excellent message passing system, as it shifts the whole functional behaviour onto timing aspects only. Microchip seems to pay attention, as they have implemented it in hardware. Creating a reliable software FIFO is also a relatively easy task, but a bit slower to run.
FIFOs are nice because if you have an upper bound for the read & write speed, with accompanying bursts, it is trivial to find the maximum buffer size you need.

Performing the same kind of modeling on 1 core means you cannot make those upper bounds as tight, resulting in more memory necessary to bridge the introduced jitter of processing.
And in many cases, people don't have a clue and just multiply buffers by a factor of 2 if the software crashes.

The 32x M0 cores can work sort of like the Propeller chip. One or two of them (maybe should have been M4F in this use case?) are application code and the rest are being used as makeshift DMA.

No I don't have a badge. Someone got the chips and excited and posted a writeup somewhere that allowed me to read an abstract.

ah, ok, sort of gossip-man. There is one in every neighborhood.

Sooner or later someone will make a huge fuss about the "latest MCU technology for the ultimate efficiency" which is in reality just something not dissimilar to this. Yes it is gossip for now though.

Multi-core systems are indeed harder to program

like this ?

I had written "interesting", but this one I posted about some time ago is a tri-core and it's too complex, and with "too complex" I mean of the level you need a huge box of pills against your headache 

You need to have a clear idea which core would do what to make use of them efficiently. FOr a 3-core system the simplest idea would be using the most powerful core for main business logic and use the two smaller ones as advanced DMA.

[NorthGuy]

Sooner or later someone will make a huge fuss about the "latest MCU technology for the ultimate efficiency" which is in reality just something not dissimilar to this. Yes it is gossip for now though.

Like Xilinx's Versal. The company which bought MIPS is probably doing something similar to this.

[bson]

And BTW, Ryzen is currently made by Globalfoundries only. They will use 7nm TSMC for future Ryzen though. TSMC and Ryzen at the same time completely invalidates this rumor.

It seems AMD switched to TSMC from GF when the latter canceled their 7nm process...

I'm also a bit surprised the Taiwanese government ever approved the Nanjing 14nm plant, at least not until 7nm is more established.

[technix]

And BTW, Ryzen is currently made by Globalfoundries only. They will use 7nm TSMC for future Ryzen though. TSMC and Ryzen at the same time completely invalidates this rumor.

It seems AMD switched to TSMC from GF when the latter canceled their 7nm process...

I'm also a bit surprised the Taiwanese government ever approved the Nanjing 14nm plant, at least not until 7nm is more established.

AFAIK there is no approval process required from Taiwan "government" (quotation marks added as per required by 2005 Anti-Secession Law of PRC) and on the mainland side it is actively encouraged and can even receive some government subsidy. Also Taiwan is land restricted while some land suitable for chip fabs in mainland is cheap and available.

[legacy]

You need to have a clear idea which core would do what to make use of them efficiently. FOr a 3-core system the simplest idea would be using the most powerful core for main business logic and use the two smaller ones as advanced DMA.

Guys using Infineon TriCore in automotive F1 are not very happy with this, besides it's also used for redundancy, rather than DMA, which isn't so smart in practice.

The redundancy has a special and dedicated hardware inside the chip, plus a "voter" special hardware (intrinsically safe).

This is a common concept you have to consider for things like high-speed trains, airplanes, formula one cars for which the Infineon TriCore makes sense, but the complexity plays bad tricks, and it's hard to be debugged, so for sure, I won't be happy to play this for the hobby .... perhaps for a well-paid job ... maybe, but it's not something that makes me happy as I am usually am when I hear the heels-shoes of the red hair secretary coming near my desk just to show her sexy elbows when she finally types the figures for my payoff (money-money honey-honey) for things for which I haven't had to waste half the money on pills for a headache during the job 

[technix]

You need to have a clear idea which core would do what to make use of them efficiently. FOr a 3-core system the simplest idea would be using the most powerful core for main business logic and use the two smaller ones as advanced DMA.

Guys using Infineon TriCore in automotive F1 are not very happy with this, besides it's also used for redundancy, rather than DMA, which isn't so smart in practice.

The redundancy has a special and dedicated hardware inside the chip, plus a "voter" special hardware (intrinsically safe).

This is a common concept you have to consider for things like high-speed trains, airplanes, formula one cars for which the Infineon TriCore makes sense, but the complexity plays bad tricks, and it's hard to be debugged, so for sure, I won't be happy to play this for the hobby .... perhaps for a well-paid job ... maybe, but it's not something that makes me happy as I am usually am when I hear the heels-shoes of the red hair secretary coming near my desk just to show her sexy elbows when she finally types the figures for my payoff (money-money honey-honey) for things for which I haven't had to waste half the money on pills for a headache during the job 

I would not count lockstepping cores as separate. Logically after entering the lockstep state they act as one core.

What I was talking about is similar to the NXP LPC4300 dual-core and triple-core MCU's. The M4F for business logic, the two M0's as advanced DMA.

[legacy]

What I was talking about is similar to the NXP LPC4300 dual-core and triple-core MCU's. The M4F for business logic, the two M0's as advanced DMA.

whatever, have you ever had a paid working experience?

[technix]

What I was talking about is similar to the NXP LPC4300 dual-core and triple-core MCU's. The M4F for business logic, the two M0's as advanced DMA.

whatever, have you ever had a paid working experience?

That was how the team used the M4F core in iMX7D in an e-reader back in my first job. Two Cortex-A9 runs Linux and mind the graphics and redrawing, while the M4F handles networking and communication (even when the main processor enters low power mode.)

[legacy]

That was how the team used the M4F core in iMX7D in an e-reader back in my first job. Two Cortex-A9 runs Linux and mind the graphics and redrawing, while the M4F handles networking and communication (even when the main processor enters low power mode.)

so you should know that it's not a piece of cake to deal with, but rather a very frustrating activity.

[technix]

That was how the team used the M4F core in iMX7D in an e-reader back in my first job. Two Cortex-A9 runs Linux and mind the graphics and redrawing, while the M4F handles networking and communication (even when the main processor enters low power mode.)

so you should know that it's not a piece of cake to deal with, but rather a very frustrating activity.

It wasn't that much frustrating really if you have a clear head on what goes where and does what. We established a separation between the two sets of cores and had a clear communication protocol. The two subsystems has separate memory areas and made use of the FIFO when tossing pointers around. I was the guy writing software for the M4F.

[bson]

AFAIK there is no approval process required from Taiwan "government"

https://www.moeaic.gov.tw/businessPub.view?lang=en&op_id_one=5&tab=1#horizontalTab

Therefore, for any investment or technical cooperation undertaken by Taiwanese citizens, juridical persons, associations and other organizations in China, shall make declaration or apply for permission to the MOEA (responsible unit: Investment Commission).
In addition, according to the provisions of Paragraph 1, Article 4 of the Regulations on Permit of Investment or Technical Cooperation in China (hereinafter referred to as the ""Regulations on Permit"") prescribed under the authorization of Paragraph 3, Article 35 of the Cross Straits Act, any of the following actions conducted by Taiwanese citizens, juridical persons, associations or other organizations in China shall be regarded as investment in China: initiating a new company or business (Subparagraph 1), increasing the capital of an existing local company or business (Subparagraph 2), acquiring the stock rights of an existing local company or business (Subparagraph 3), or expanding a branch or business (Subparagraph 4). To conduct such action in China, a Taiwanese investor shall make a declaration or submit an application for permission to the Commission in advance.

Building a plant certainly is both technical cooperation and increasing capital...

[coppice]

AFAIK there is no approval process required from Taiwan "government"

https://www.moeaic.gov.tw/businessPub.view?lang=en&op_id_one=5&tab=1#horizontalTab

Therefore, for any investment or technical cooperation undertaken by Taiwanese citizens, juridical persons, associations and other organizations in China, shall make declaration or apply for permission to the MOEA (responsible unit: Investment Commission).
In addition, according to the provisions of Paragraph 1, Article 4 of the Regulations on Permit of Investment or Technical Cooperation in China (hereinafter referred to as the ""Regulations on Permit"") prescribed under the authorization of Paragraph 3, Article 35 of the Cross Straits Act, any of the following actions conducted by Taiwanese citizens, juridical persons, associations or other organizations in China shall be regarded as investment in China: initiating a new company or business (Subparagraph 1), increasing the capital of an existing local company or business (Subparagraph 2), acquiring the stock rights of an existing local company or business (Subparagraph 3), or expanding a branch or business (Subparagraph 4). To conduct such action in China, a Taiwanese investor shall make a declaration or submit an application for permission to the Commission in advance.

Building a plant certainly is both technical cooperation and increasing capital...

Its not just the Taiwan government which needs to agree. The US, Japanese and other companies supplying the key 14nm capable equipment all need export licences to be able to ship such advanced technology. Not long ago they wouldn't have been able to obtain those licences to build a cutting edge plant in China, but things change.

[bson]

Its not just the Taiwan government which needs to agree. The US, Japanese and other companies supplying the key 14nm capable equipment all need export licences to be able to ship such advanced technology. Not long ago they wouldn't have been able to obtain those licences to build a cutting edge plant in China, but things change.

Well, Taiwan AFAIK still has the "two generations behind" policy, and to be frank 14nm isn't exactly cutting edge.  So it's two generations behind 10nm and 7nm, but given 7nm is still very much bleeding edge I'm a bit surprised they approved it.  And 10nm isn't exactly volume stuff. But I suppose it means they were convinced 7nm is in regular production or would be by the time Nanjing is.