Author Topic: CPLD or FPGA, please help  (Read 20172 times)

0 Members and 1 Guest are viewing this topic.

Offline asmi

  • Super Contributor
  • ***
  • Posts: 2728
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #100 on: January 30, 2018, 11:32:25 pm »
In the end, it doesn't matter.  ISE doesn't support the new chips and Vivado doesn't support the old ones (of which I have several boards).  It is imperative to have both versions running.
ISE supports 7 series chips.

Offline NorthGuy

  • Super Contributor
  • ***
  • Posts: 3137
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #101 on: January 31, 2018, 12:15:37 am »
Vivado looks very slow to me, slower than ISE without any doubts. My natural tendency is to recompile often, so Vivado drives me nuts.
 

Offline asmi

  • Super Contributor
  • ***
  • Posts: 2728
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #102 on: January 31, 2018, 12:57:34 am »
Vivado looks very slow to me, slower than ISE without any doubts. My natural tendency is to recompile often, so Vivado drives me nuts.
Like I said, you can use ISE for 7 series if you want.
I only ever do a full P&R after all testbenches are successfully completed, so I spend most of the time in simulator, and it "recompiles" code quite quickly. "Recompile often" is a bad approach, because as your project grows so will the P&R time, and at some point you will spend most of the time waiting. This doesn't strike me as most efficient approach. I do know where this approach comes from as I'm professional software developer, and there compilation tend to be rather quick, but I made a point to change my habits when it comes to HW development.

Offline lawrence11Topic starter

  • Frequent Contributor
  • **
  • Posts: 321
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #103 on: January 31, 2018, 05:39:12 am »
ISE re-dowload.

So who here has used this magical MCB?

I will see what kind of pinout this represents and how bad it is to design a pcb for it.

Right here might be the deciding factor, PCB price.

One thing leads to another, into the No Go zone once again.

 

Offline asmi

  • Super Contributor
  • ***
  • Posts: 2728
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #104 on: January 31, 2018, 06:20:38 am »
Right here might be the deciding factor, PCB price.
10 4 layer boards 10x10 cm with 0.1/0.1 mm and 0.2 mm drills, ENIG finish, controlled impedance (requirement for high-speed traces) is about $140. Same specs but 6 layers is about $200. Delivery charge is extra (in my case it was $30 to ON, Canada). I doubt you can make x32 DDR3 layout on a 4 layer board (I couldn't do it even for x16 bus), so count on 6 layer board as it will give you a lot of freedom and will make layout much easier.

High-speed layout is not particularly difficult but requires you to read, understand and follow layout requirements like length match groups, fly-by routing and spacing between traces to keep crosstalk in check. All of that is described in HW guides and appnotes, so information is out there, but - just like with BGA packages - it has a reputation of being "very hard" in the community (and I was guilty of thinking the same until I actually did this). It's not hard if you understand what you're doing and why - and aforementioned docs do a great job of explaining that. DDR3 on my board worked perfectly at full speed (400 MHz) on a first try, and it had even less design margin because I use low-power DDR3L module (voltage swing is smaller than in "normal" DDR3 mode).

Offline lawrence11Topic starter

  • Frequent Contributor
  • **
  • Posts: 321
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #105 on: January 31, 2018, 10:41:27 am »
This FPGA thing is a bit complicated.

Why is this IP core taking so much pins?

What is an acceptable pin count for what I wanna accomplish? I need to fill up a single DDR3 chip that is X16. I dont read while I write, I guess this is not bidirectionnal in my case.


IO Utilization:
  Number of bonded IOBs:                       239 out of     186  128% (OVERMAPPED)
    Number of LOCed IOBs:                       52 out of     239   21%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      32    0%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3%
    Number used as BUFIO2s:                      1
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       3 out of      16   18%
    Number used as BUFGs:                        2
    Number used as BUFGMUX:                      1
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:        24 out of     200   12%
    Number used as IODELAY2s:                    0
    Number used as IODRP2s:                      2
    Number used as IODRP2_MCBs:                 22
  Number of OLOGIC2/OSERDES2s:                  47 out of     200   23%
    Number used as OLOGIC2s:                     0
    Number used as OSERDES2s:                   47
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         1 out of       4   25%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                1 out of       2   50%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            1 out of       2   50%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Mapping completed.
See MAP report file "mig_39_2_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   2
Number of warnings :   0

Section 1 - Errors
------------------
ERROR:Pack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device.  Please check the Design Summary section to see which resource requirement for
   your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as
   their packing might not have been completed.
« Last Edit: January 31, 2018, 10:43:12 am by lawrence11 »
 

Offline asmi

  • Super Contributor
  • ***
  • Posts: 2728
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #106 on: January 31, 2018, 02:07:22 pm »
This FPGA thing is a bit complicated.

Why is this IP core taking so much pins?
It looks like you're trying to externally expose AXI Slave bus :D AXI is designed to be used only inside the FPGA for interconnects between internal subcomponents, but never exposed to outside world.

Offline NorthGuy

  • Super Contributor
  • ***
  • Posts: 3137
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #107 on: January 31, 2018, 03:07:35 pm »
"Recompile often" is a bad approach, because as your project grows so will the P&R time, and at some point you will spend most of the time waiting. This doesn't strike me as most efficient approach.

"Recompile often" is a very good approach. Of course, it doesn't live well with overbloated tools. ISE is quite overbloated too, just not as much as Vivado.

The idea that P&R is inherently slow doesn't hold water. Even if you place everything manually, it'll still be slow.
 

Offline asmi

  • Super Contributor
  • ***
  • Posts: 2728
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #108 on: January 31, 2018, 03:17:42 pm »
"Recompile often" is a very good approach.
Of course you're going to defend your approach ;D

What's the point of it anyway? One doesn't need P&R to run sims (except in very rare cases where bad placement caused timing issues), and normally if I do P&R that means it's already passed functional verification and so I'm reasonably certain it will work in hardware on the first try. I only make exception from TDD approach when working with some external chip with not very good datasheet, and so I need to use ILA to see what it actually does.

Offline NorthGuy

  • Super Contributor
  • ***
  • Posts: 3137
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #109 on: January 31, 2018, 03:57:54 pm »
"Recompile often" is a very good approach.
Of course you're going to defend your approach ;D

You bet.

What's the point of it anyway? One doesn't need P&R to run sims (except in very rare cases where bad placement caused timing issues), and normally if I do P&R that means it's already passed functional verification and so I'm reasonably certain it will work in hardware on the first try.

I don't know. You brought the P&R up, not me. You said:

"Recompile often" is a bad approach, because as your project grows so will the P&R time, and at some point you will spend most of the time waiting.

Now you say that you only need P&R very rarely. Ok. Let it be. Are you implying that synthesis in Vivado is quick?

 

Offline lawrence11Topic starter

  • Frequent Contributor
  • **
  • Posts: 321
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #110 on: January 31, 2018, 04:47:22 pm »
I just created a new file.

Common procedure----->new_new project, chose my target, Tools---->Core Generator

Then once in the new Core menu, new Project, make sub-folder, and configure my chip with the MCB GUI.

I am using 16x default, with a 256 pin BGA.

I never saw the term "AXI" from beginning to end.

How do I turn this off.

Ok I see now,

https://www.xilinx.com/support/documentation/ip_documentation/mig/v3_9/ug416.pdf

in Click the Enable AXI check box to add an AXI4 user interface to all MCBs (this option
is only available for Verilog designs). Otherwise, the MIG design is generated with the
standard (or Native) user interface by default
. Select a memory standard from the
Memory Type drop-down menu for each MCB that implements a memory interface
(only DDR2 and DDR3 are available when using an AXI4 interface). Click Next.

Now, can somebody tell me where is this "native" user interface? How come I dont get this inferface yet this causes my compile to fail WTF?


In this cluttered bunch of files.
« Last Edit: January 31, 2018, 05:33:17 pm by lawrence11 »
 

Offline nctnico

  • Super Contributor
  • ***
  • Posts: 26755
  • Country: nl
    • NCT Developments
Re: CPLD or FPGA, please help
« Reply #111 on: January 31, 2018, 05:26:16 pm »
Vivado looks very slow to me, slower than ISE without any doubts. My natural tendency is to recompile often, so Vivado drives me nuts.
Like I said, you can use ISE for 7 series if you want.
I only ever do a full P&R after all testbenches are successfully completed, so I spend most of the time in simulator, and it "recompiles" code quite quickly. "Recompile often" is a bad approach, because as your project grows so will the P&R time, and at some point you will spend most of the time waiting. This doesn't strike me as most efficient approach. I do know where this approach comes from as I'm professional software developer, and there compilation tend to be rather quick, but I made a point to change my habits when it comes to HW development.
I agree when it comes to developing HDL code. When I make a new module I simulate it before integrating it into the design. That usually saves quite a few P&R cycles but you can't avoid them all. Sometimes I need to tweak the map parameters to make a design P&R quicker and/or meet timing but it takes a lot of P&R cycles to find a good value. The right map parameters can mean the difference between P&R in 10 minutes + meeting the timing requirements and running for 8+ hours and not meeting the timing requirements.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline mrflibble

  • Super Contributor
  • ***
  • Posts: 2051
  • Country: nl
Re: CPLD or FPGA, please help
« Reply #112 on: January 31, 2018, 06:29:12 pm »
quick post. during installation you can select the components you want. For example webpack vs system edition (or something lkike it). Anyways, the XPS system thingy is not part of all install types. But core generator should be part of it.

Short version: from IE you should be able to start core generator, from which you can build your MIG.
 

Offline lawrence11Topic starter

  • Frequent Contributor
  • **
  • Posts: 321
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #113 on: January 31, 2018, 06:39:21 pm »

I'll check later for XPS...Maybe...Maybe never

Where do I find the AXI4 config file, the config thingy that will change things and let me compile.

You know what I mean...The config file for AXI4 that doesnt let me compile a bitfile.

Nevermind the other stuff, XPS is gone, was removed by xilinx. Its just a bullshit 3 letter word that you need to pay for.

I have the CoreGenerator, I have this, I can create a DDR project but I cant compile a bitfile because of this dam by default AXI settings, it seems like I dont get
my advertised GUI settings (wich allows trial and error testing out stuff) for the AXI. So I am now in search of some sort of file where I comment out things to make it equivalent to the AXI GUI experience?

This FPGA thing is a bit complicated.

Why is this IP core taking so much pins?
It looks like you're trying to externally expose AXI Slave bus :D AXI is designed to be used only inside the FPGA for interconnects between internal subcomponents, but never exposed to outside world.

I am trying the exact opposite of that, I DONT want to expose the AXI slave Bus to the outside world, I would like it to be NOT exposed to the outside world.


« Last Edit: January 31, 2018, 06:54:20 pm by lawrence11 »
 

Offline asmi

  • Super Contributor
  • ***
  • Posts: 2728
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #114 on: January 31, 2018, 08:24:30 pm »
No offence, but you seem to have no idea what are you talking about.
AXI is a bus that is used to issue commands to the memory controller. So whatever component(s) you design will connect to this bus and issue commands - hence your component will have AXI Master bus connector. On your screenshot I see wires like "s_axi_*" - these are wires that belong to AXI bus.
Go the the ARM website and download AXI4 specification - it explains how this bus works, and how to use it.
Alternatively you can use "native" interface - for 7 series devices it's described in document UG586, page 92 and below. But I never actually used it as I prefer using AXI because it's more universal, so I can't help you here. At least in Vivado MIG generates an example design along with the actual core when you invoke it, so you might want to check if it's the same for MIG in ISE - and if it is, study it's code (along with reading documentation) to get an idea how to use the thing.
« Last Edit: January 31, 2018, 08:30:18 pm by asmi »
 

Offline lawrence11Topic starter

  • Frequent Contributor
  • **
  • Posts: 321
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #115 on: January 31, 2018, 08:39:38 pm »
I dont need to read about AXI just to generate a bitfile example from a GUI.

I need to know where I make my pin count lower so I can compile.
 

Offline lawrence11Topic starter

  • Frequent Contributor
  • **
  • Posts: 321
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #116 on: January 31, 2018, 09:37:44 pm »
Sorry, sometime you guys just get on my nerves, sometimes these comments are not helping, but I know its just because you never went through these unlucky same and bullshit problems a noobie faces.

I have to read about AXI but its just bullshit this FPGA software is like Catia on steroids x10. All those dam icons and 100 page pdf's everywhere I'm pissed off its not easier.

In a rage, I said, one last time before I try Lattice software and there it was, it was like in the image.

I managed to get the AXI thing to look like it should.

You have to create your project inside core generator, from scratch,  thenopen it with ise or just click the icon inside that project.

Not by creating an ISE project ( choose device), then add an IP core( with same device). This makes AXI dissapear, not there nor selectable.

Not like this video, and not like in one of the documents ( there's 2 different ones), one basicly shows the wrong way, then they show you the AXI Figure and you think you missed something.

Really a big mess.



I now see AXI, still I cant compile, I have same errors. but I am seeing it.

« Last Edit: January 31, 2018, 10:19:12 pm by lawrence11 »
 

Offline james_s

  • Super Contributor
  • ***
  • Posts: 21611
  • Country: us
Re: CPLD or FPGA, please help
« Reply #117 on: February 01, 2018, 12:53:47 am »
We're not trying to get on your nerves, we're trying to help, but you're not listening. You keep trying to skip ahead to the end and want a simple answer to a very complex question. You need to take a few steps back and take the time to learn the HDL you wish to use, and then learn how to use IP cores. It looks like you're trying to build a standalone IP core, that's not how these are designed to work. What you should do is have a top level file which has all the IO that interfaces to the physical world through pins on the device, then within that top level file you have modules such as the IP core(s) you wish to use and other functionality that is "wired" together via the top level file. Attempting to rush to the end is only going to lead to frustration, it's like trying to jump right into calculus without bothering to learn basic arithmetic and algebra.
 

Offline lawrence11Topic starter

  • Frequent Contributor
  • **
  • Posts: 321
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #118 on: February 01, 2018, 04:46:40 am »
No offence, but you seem to have no idea what are you talking about.
AXI is a bus that is used to issue commands to the memory controller. So whatever component(s) you design will connect to this bus and issue commands - hence your component will have AXI Master bus connector. On your screenshot I see wires like "s_axi_*" - these are wires that belong to AXI bus.
Go the the ARM website and download AXI4 specification - it explains how this bus works, and how to use it.
Alternatively you can use "native" interface - for 7 series devices it's described in document UG586, page 92 and below. But I never actually used it as I prefer using AXI because it's more universal, so I can't help you here. At least in Vivado MIG generates an example design along with the actual core when you invoke it, so you might want to check if it's the same for MIG in ISE - and if it is, study it's code (along with reading documentation) to get an idea how to use the thing.

I tried this before but it seems like I have to buy the board to get the examples for the DDR2.

https://www.xilinx.com/products/boards-and-kits/ek-s6-sp601-g.html#documentation

There is missing files from the DDR2 example design.
« Last Edit: February 01, 2018, 05:58:35 am by lawrence11 »
 

Offline mrflibble

  • Super Contributor
  • ***
  • Posts: 2051
  • Country: nl
Re: CPLD or FPGA, please help
« Reply #119 on: February 01, 2018, 06:00:52 am »
Not a 100% match of what you want, but the required steps are similar.
You can take a look at the board files + MIG related stuff. Maybe it has enough
info in it for you such that you don't have to RTFM. At least you don't have to
buy anything to get board files. ;)

https://reference.digilentinc.com/nexys4-ddr/advmb
https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-4-ddr/nexys4ddr_mig_prj.zip
https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/

 

Offline mrflibble

  • Super Contributor
  • ***
  • Posts: 2051
  • Country: nl
Re: CPLD or FPGA, please help
« Reply #120 on: February 01, 2018, 07:05:06 am »
I can confirm, from personal experience, that AXI is a particularly confusing specification for those new to FPGAs.
If the AXI avoidance score is really high ... you don't have to use AXI.

In ISE in core generator select the "Show older versions" (or something to that effect, it's been a while). Then you will also see the older non-AXI MIGs. In the past I've done exactly that because at the time I didn't need AXI for any other component, and the old school MIG flavor was less work to use in that project.

For Vivado I think you can do something similar. See for example:
https://forums.xilinx.com/t5/Memory-Interfaces/Looking-for-native-user-interface-option-in-MIG-7-Vivado-v2-3/td-p/550963
 

Offline lawrence11Topic starter

  • Frequent Contributor
  • **
  • Posts: 321
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #121 on: February 01, 2018, 07:59:35 am »
I can confirm, from personal experience, that AXI is a particularly confusing specification for those new to FPGAs.

Annoying is it? All this messing around just to use some DDR3... Really a pain in the a**.

I follow a procedure from a pdf.

So Asmi was right, the AXI4 bus is acting stupid and not giving me a default randomized pinout according to my GUI requirements that can be compiled and played with. :wtf: 

 Please help. I wanna "connect my axi bus to something". Or just not use AXI. The goal of me needing to use an FPGA is to buffer an image frame, and analyze with a microcontroller. Get this done  and over with.

 Thank you.
 

Online Someone

  • Super Contributor
  • ***
  • Posts: 4510
  • Country: au
    • send complaints here
Re: CPLD or FPGA, please help
« Reply #122 on: February 01, 2018, 08:59:49 am »
All this messing around just to use some DDR3... Really a pain in the a**
If the vendor IP is so hard to use then will it be much easier to simply write your own DDR controller?
 

Offline asmi

  • Super Contributor
  • ***
  • Posts: 2728
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #123 on: February 01, 2018, 02:36:06 pm »
So Asmi was right, the AXI4 bus is acting stupid and not giving me a default randomized pinout according to my GUI requirements that can be compiled and played with. :wtf: 

 Please help. I wanna "connect my axi bus to something". Or just not use AXI. The goal of me needing to use an FPGA is to buffer an image frame, and analyze with a microcontroller. Get this done  and over with.
You keep trying to brute-force this without much thinking. Take a step back and try to understand what are you going, and you will see a problem. AXI bus is can't possibly "act" - it's all of your doing.

Offline asmi

  • Super Contributor
  • ***
  • Posts: 2728
  • Country: ca
Re: CPLD or FPGA, please help
« Reply #124 on: February 01, 2018, 02:45:51 pm »
If the AXI avoidance score is really high ... you don't have to use AXI.
You will have to learn AXI sooner or later as just about anything in Xilinx IP world uses this bus. Want video streaming? Here's AXI Stream. Need to connect some (relatively) slow peripheral to Microblaze/Zynq CPU? That's what AXI Lite is for. Need to do high-bandwidth data exchange with some other component inside your system? AXI Full exists just for that.
The bus might seem intimidating at first glance due to sheer amount of signals, but once you understand the reasoning behind them all, it becomes quite clear. The only real source of confusion I can see is relative timing of WA/WD and RA/RD channels.
Also Vivado provides a tool that can generate very well commented boilerplate stubs for any of aforementioned variations of AXI bus, as well as excellent AXI Verification IP which makes developing testbenches orders of magnitude easier than it used to be in the past.


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf