CPLD or FPGA, please help

[lawrence11]

No problem learning it. No choice there. .

The software should invite me into a graphical pinning out of the bus after I set up the DDR. Thats is the problem.

I just need to know where I reroute and connect the axi4 BUS to external things.

Theres like 32 wide address bus and 32 wide data bus and a few other pins. In fact, I like this Bus, it is reminiscent of SRAM.

[NorthGuy]

All this messing around just to use some DDR3... Really a pain in the a**

If the vendor IP is so hard to use then will it be much easier to simply write your own DDR controller?

Reading JEDEC DDR3 specs is substantially bigger effort than reading AXI4 specs.

The OP seems to have an inclination to avoid reading, which certainly makes even simpler things much harder.

[lawrence11]

I have no problem reading.

https://www.xilinx.com/support/documentation/ip_documentation/mig/v3_9/ug416.pdf

All files I read never tell me where I should connect the interface. In fact, they show me a graphical configuration that I never see when I am in native mode.

Where are those 64+ bus connections that are assumed lost and not connected internally, in what file? I will go there and connect those connections to pins( user logic)

It will be more clear to me once I know the exact file I should study. I  will track down their names and what they do and what pins I want them to relate to.

[lawrence11]

Ok never mind this DDR for now.

I will pay attention on the upgrades, one day I will learn it once they make a more user friendly software  that has actual GUI, and a real BUS to PIN interface.

This will get done with SRAM.

[mrflibble]

... one day I will learn it once they make a more user friendly software  that has actual GUI, and a real BUS to PIN interface.

So, roundabout the introduction of DDR8 then.

[james_s]

Don't hold your breath. FPGA development is an esoteric field, it is inherently complex enough that the software to do it is not going to be super easy to use. It's aimed at professional engineers who have the training and experience to use it effectively, the hobby community is very small.

[lawrence11]

Not holding my breath. I`d say by the time they make DDR5 or 6. DDR2 is almost 20 years old and its used today.

Maybe a DDR manufacturer will pay them to make a really easy GUI that allows for plug and play.

Maybe when I need the upgrade I will pay Lattice for a really newbie friendly libary that is plug and play. Apparently its ''low cost''.

[asmi]

Maybe a DDR manufacturer will pay them to make a really easy GUI that allows for plug and play.

You're using the software that has been officially abandoned by the vendor at least 4 years ago (when they transitioned to Vivado, which is the tool they are actively working on right now). There will NEVER be a single "Do it good!" button you seem to be looking for because flexibility that FPGAs provide always comes at expense of complexity.

Maybe when I need the upgrade I will pay Lattice for a really newbie friendly libary that is plug and play. Apparently its ''low cost''.

They are even worse than Xilinx. And their DDR controller costs $$$.

Last point - FPGA are beginner-friendly, but only for those beginners who are willing to learn a lot of new things and concepts which are unique to FPGA world.

[james_s]

Who is the market target for a really easy to use DDR IP core? How does that translate into profit for the company producing it? Keep in mind the development effort could easily exceed many tens of thousands of dollars.

Lots of people already using DDR RAM with FPGAs, I posted links to at least two controllers earlier.

[nctnico]

Who is the market target for a really easy to use DDR IP core? How does that translate into profit for the company producing it? Keep in mind the development effort could easily exceed many tens of thousands of dollars.

Lots of people already using DDR RAM with FPGAs, I posted links to at least two controllers earlier.

IMHO the built-in DDR memory controller in the Spartan6 is pretty easy to work with and you can choose what kind of memory widths it has. Over a decade ago I wrote my own DDR controller from scratch and that was quite a bit of work to say the least.

[maginnovision]

Why not just learn first and then do it properly? I'm sure by learning what you should know first will actually save you time including the learning time.

[BrianHG]

Who is the market target for a really easy to use DDR IP core? How does that translate into profit for the company producing it? Keep in mind the development effort could easily exceed many tens of thousands of dollars.

Lots of people already using DDR RAM with FPGAs, I posted links to at least two controllers earlier.

IMHO the built-in DDR memory controller in the Spartan6 is pretty easy to work with and you can choose what kind of memory widths it has. Over a decade ago I wrote my own DDR controller from scratch and that was quite a bit of work to say the least.

It took me 3 solid months to get my SODIMM 8-port (4 read ports, 4 write ports), with adaptive variable same page burst length DDR2 controller working in Quartus 9.2.  It was a fluke that the PCB cad-ing went perfectly, but then again, I also wrote a tool which took both my netlist from Protel99se and Quartus's pinmap in the assignments file and filled it in guaranteeing no pinout mistake other than the possibility of using a wrong color coded bank in the FPGA as I was using variable voltages.  The biggest annoyance was the read latch clock since I wanted multiple different frequency module support and I ignored the DQS on reads opting for the loss of the possible extra 1/2 clock shorter read latency.

[NorthGuy]

I think my idea would be cooler and higher quality if I used DDR, but that was when I thought this was GUI 100%

I would rather think about the future. Imagine you succeed. Then few months and $2,000 later you get a working board which can accept an HDMI stream, write a frame to DDR memory, then gives you an AXI stream to let you read back the picture you have just saved few milliseconds ago. Is that what you want/need? What are you going to do with it? How is it better than the picture you had before saving? Is that short delay between saving and reading back was worth the effort?

[james_s]

For the most part you should just forget about the GUI. It's ok for instantiating IP components but once you've created that, you will virtually always want to connect them together using your HDL of choice. The FPGA software has a schematic capture feature but it's really just a gimmick, beyond extremely simple projects it only makes it far more tedious and time consuming to develop and debug. If you don't take the time to learn VHDL or Verilog you will never get very far with this.

[BrianHG]

I've only used the GUI for the Top hierarchy in Quartus.  It basically automatically made 1 or 2 of my main verilog modules into block with inputs on the left and IOs on the right and I just placed the IO pins at each port.  Everything else inside those 1-2 modules was all in HDL except for the occasionally added PLL instance which I might opt to place on the top or everything instead of inside the HDL.  This became useless once I had to begin to use software reconfigurable PLLs.  All in HDL was the only way after all those control signals had to be wired up.

Note this was back in the mid 2000s and it was how I was taught at the time.  Quartus still seems big on providing fancy illustrated GUI modules for their IP.  It may only be useful for illustration purposes or if you are making a project just to simulate that 1 module with Quartus' internal simulator which was abandoned back in version 10.0.  Today, it just gets the in the way of full HDL coding and may only have a slight purpose in school work as a small stepping stone between seeing wired HDL modules in the GUI, then, learning how to 'wire' and 'assign' connections between such modules in your own HDL code without the GUI.

[james_s]

Things have not changed much in that regard so far as I've seen. When I was just getting my feet wet with CPLDs the schematic capture tool was a cool way to play with some basic logic and blink some LEDs very early on. I even went so far as to recreate most of the original Atari Pong arcade game on a CPLD using the schematic. It was partially working but had some issues, I soon realized how tedious the schematic was and gave up on that particular project. Outside of the wizards for setting up IP blocks like clock PLLs and RAM/ROM instances the GUI is pretty useless.

[asmi]

For the most part you should just forget about the GUI. It's ok for instantiating IP components but once you've created that, you will virtually always want to connect them together using your HDL of choice. The FPGA software has a schematic capture feature but it's really just a gimmick, beyond extremely simple projects it only makes it far more tedious and time consuming to develop and debug. If you don't take the time to learn VHDL or Verilog you will never get very far with this.

I disagree. While I do spend most of time in the code editor and simulation window, I do like diagrams in Vivado as a great way to visualize all interconnect so you can quickly see the entire system "at a glance". This is especially useful when I open some kind of sample project, or even my own project that I didn't touch for a while. In recent versions Xilinx finally added ability to directly instantiate your code modules in the diagram without creating IP package.

Connecting multiple AXI buses in HDL is quite a miserable and error-prone experience due to sheer amount of signals. Also Vivado automatically generates AXI interconnects when needed (for example when you want to connect multiple masters to the same bus, or when different parts of AXI bus need to have different clocks). So it's definitely useful, especially so if your design is only going to use pre-existing IPs (which are plentiful - even webpack edition contains almost 200 free IPs!) as it allows you to create entire system without writing a single line of HDL code. And even commercial IPs provide evaluation versions for free, so you can use them as "known good" code to test your newly built hardware, so that when time will come to develop your own IPs you will be certain that hardware works. For example, when I assembled my first Artix board with DDR3, it took me literally few clicks of a mouse to create a test system that allowed me to confirm that DDR3 indeed works.

[KE5FX]

A few random thoughts in no particular order:

1) Vivado is faster and better in pretty much every way than ISE, in my experience.  That was not true a couple of years ago, but at this point I don't miss ISE at all.  If your project takes longer to build in Vivado than in ISE, make sure you're using comparable settings and taking advantage of out-of-context IP synthesis.

2) Consider Hyperram if DRAM routing or controller complexity is a problem for any given reason.  Sounds like you may have to do some interleaving, either way.

3) Start with an eval/demo board or trainer.  Do not attempt to bring up hardware at the same time you're getting your first FPGA project going, especially not one as complex as this one sounds like.

4) No matter what you need to do, there is almost certainly either an existing tutorial somewhere for it, or a ready-made project somewhere on Github.  Do not attempt to build complicated stuff from scratch when you're not entirely sure of what you're doing.

5) There will probably never be a time when FPGAs and their toolchains aren't stupefyingly complex, slow, and annoying.  It is what it is.  Again, your best defense is to start with an existing hardware platform, even if only for tutorial purposes.

[lawrence11]

The problem with Vivaldo is that it needs 50$ IC's.

So now we got a PCB price problem and a component price problems.

Its funny how when I  am electronics amateur entrepreneur I transform myself into a penny pincher, I'm not like this in real life.

But when it has to do with my design, I like it to be cheap.

I dont know about you LOL...

[Someone]

The problem with Vivaldo is that it needs 50$ IC's.

Digikey have single quantity Artix devices starting from $26, once spartan 7 series are in volume production they should appear well under that. The market is fairly competitive so you get what you pay for, there aren't large cheap FPGAs from any vendor.

[NorthGuy]

The problem with Vivaldo is that it needs 50$ IC's.

Digikey have single quantity Artix devices starting from $26, once spartan 7 series are in volume production they should appear well under that.

Judging by what prices they have now, spartans won't be much cheaper than artixes.

[asmi]

Judging by what prices they have now, spartans won't be much cheaper than artixes.

Right now on DK Canada XC7S50-1FGGA484C is 72.34 CAD, while equivalent Artix (XC7A50T-1FGG484C) is 109.59 CAD. So S7 is about 34% cheaper. I expect the smallest S7 (6K logic cells in 4-layer-friendly FTGB196 package) will be about 15-20 CAD for singular quantity.