CPLD or FPGA, please help

[james_s]

"always@(posedge clk) begin" is the start of a process statement. This creates a D-type flip-flop triggered on the rising edge of the clock pulse, which in this case is a signal called "clk".

Teaching you Verilog or VHDL is beyond the scope of a forum post. If you read some tutorials that should answer most of these questions. I liked the free e-book "Free Range VHDL", perhaps someone can point to a similar lesson for Verilog.

[BrianHG]

Last paragraph, remember, all you 20 outputs will be computed in 1 clk.  All in parallel.  All the 'if' and 'else' all happen simultaneously.  But, there is still that 1 clk delay.  The PLD isn't instant.

What I am saying if a you are searching for a white pixel.  Once the pixel comes into the PLD and the clock cycles, your output will be set.  This may be fine for you.  Then everything is ok.

Say if you want to change that white pixel to another color, however, once you decoded your output pin, the next newer pixel is already coming into your PLD, the white pixel has already left.  I was only suggesting a way to output your white decoding output pin simultaneously with the white pixel data which came into the PLD at the previous clock by piping the 24 bit color data through the PLD as well, delaying it by 1 clock, so you can modify or mask out that white pixel data based on one of your 20 pin decoded outputs.  You do not need to do this unless you wish to manipulate the video picture data based on your 20 decoded outputs in perfect synchronicity.


Piping the entire 24 bit pixel through the FPGA means if there are enough gates, you can manipulate the video picture data, not just decode your 20 outputs.  Like, change contrast or color, even sharpen/blur/saturation and tint the image if your FPGA has enough gates in it.

[BrianHG]

Verilog basics and tutorial: http://www.asic-world.com/verilog/index.html
Basic guide to Verilog syntax and language structure, variable types, commands + examples.

On how to type you verilog programs into Xilinx or Quartus, just Google how to program verilog in Xilinx/Altera Quartus, or even search on youtube for a visual on how to enter code in Xilinx/Quartus.

[agehall]

Just build the code for the things you need, simulate and test it. If the compiled code fits in a CPLD - go for that. If not, you need an FPGA.

But I find it very hard to believe that you need anything other than a CPLD for this. As others have said, you are spending way too much time on a trivial aspect of your project - just get on with it and it will become very clear what you actually need.

[iMo]

I am a bit new with both of these to be honest, I was just watching some yt videos right now.

You have to start with something much simpler..
Buy a cheap CPLD board, learn the basics, try with verilog and get familiar with the tools/develepment chains..
A long way to go..

[agehall]

I am a bit new with both of these to be honest, I was just watching some yt videos right now.

You have to start with something much simpler..
Buy a cheap CPLD board, learn the basics, try with verilog and get familiar with the tools/develepment chains..
A long way to go..

My first CPLD project was a protocol converter for the CD exchanger in my car. Maybe not the prettiest VHDL, but it worked just fine. It doesn't have to be that hard, just break things down and work thru the problems...

[lawrence11]

I thank everybody for their participation.

For curriosity: This is a comment from the xilinx forums.

I think this design will call for an FPGA. I doubt that a CPLD (at least from Xilinx's range) will be big enough to handle 100 3-byte combinations, whereas their smallest "new" FPGA (Spartan 7 XC7S6) would do it easily.

 

Have you got a preferred implementation language (VHDL or Verilog)? You could probably do it in C via HLS if you had to, but HLS isn't really designed for toggling pins.

[james_s]

VHDL and Verilog are the two big HDLs (Hardware Description Language) used to develop for CPLDs and FPGAs. Verilog is more widely used in professional circles in the US while VHDL is more popular in Europe and academics. VHDL also seems to have a lot more hobbyist support and is my personal preference. Despite the passionate debates some will have, there is really no clearly superior language, it's like debating English vs German, they can both describe the same thing. Have a look around, try some basic tutorials in both and pick the one that makes the most sense to you.

Forget about programming languages like C, you're not writing a program, you're describing digital hardware. You have to get into the right mindset, a hardware designer, visualize logic gates, flip flops, latches, counters and such. You're using a special language to describe a schematic, you're not writing a sequential program. Tell yourself that as many times as you have to in order for it to sink in.

[NorthGuy]

I think this design will call for an FPGA. I doubt that a CPLD (at least from Xilinx's range) will be big enough to handle 100 3-byte combinations, whereas their smallest "new" FPGA (Spartan 7 XC7S6) would do it easily.

Spartan-7 has 6-input LUTs, so 24-bit input can be fed to 4 LUTs (24/6) plus one LUT to get the combined inputs from the first 6. It is 5 LUTs per color to find a match. 5 LUTs x 50 colors = 250 LUTs. Plus 20 to 100 LUTs for output. Thus you'd need about 350 LUTs. A good portion of these can be eliminated by the tools if there are colors with common bytes.

XC7S6 has about 3700 LUTs. Looks like huge overkill to me.

[james_s]

Just to put things in perspective, a tiny by modern standards Altera EP2C5T144C8 FPGA can contain a complete 8 bit computer system with a Z80 soft core, ROM, VGA controller, serial ports, SD card interface and boot the full fledged operating system CP/M with the only external semiconductor being a RAM chip and that consumes only about 70% of the FPGA fabric. When comparing to 74xx series TTL logic a small modern FPGA is a bit like a breadboard the size of a tennis court.

[lawrence11]

I understand Brian

[james_s]

You have the same learning ability as many of us, it's just a matter of taking the time. I spent probably 2 years tinkering with VHDL before something clicked and I finally got to where I could write the code for a project, fix a handful of typos and other dumb errors and it would compile and more or less work. FPGA development is difficult and has a steep learning curve, that's why so few people do it.

Xilinx and Altera are the two I'm familiar with, I've gone back and forth and have not found a real clear winner, both have quirks and advantages. Overall I think I like Altera's Quartus II a bit better than Xilinx ISE, and the (clone) programming dongles for the Altera hardware are much smaller and cheaper so that is another perk. Again don't spend too much time worrying about which vendor to use, the products are roughly similar, they all use pretty much the same code, it's easy to port from one to the other. The choice largely comes down to which software package you like better since you are locked into using the software supplied by the hardware vendor. Quartus and ISE both have free versions for personal use, keep in mind that at least with Altera you have to use an older version for some of the older parts that are still popular amongst hobbyists. 13.0 SP1 is the last version to support the popular Cyclone II series of FPGAs.

[james_s]

Go to digikey.com and use the parametric search, there are loads of CPLDs and FPGAs that meet your criteria. At this stage I would suggest using a basic development board rather than bothering with a bare chip, it will save a lot of time and the cost is similar. I've used the Xilinx XC9500 and Altera Max series CPLDs with good results. The Altera Cyclone II and Cyclone IV FPGAs are inexpensive and readily available if you need to step up to something larger. For now just buy something cheap and play with it.

[james_s]

What do you mean? The XC9500 CPLDs have IO pins that are 5V tolerant and 3.3V native, most of their FPGAs have IO that is selectable between several formats. Parts made by all the main vendors have similar specs in that regard.

[BrianHG]

Your going for the Altera Max 10 10M02SCE144C8G.
Nice choice, no boot-prom needed.  Only a single 3.3v supply.  144pin QFP.  101 IOs,
Don't need your static ram controller, just wire the PLD directly to the ram and program direct access.  Unless it is DRAM, then you need a DRAM controller firmware if you are trying to do a bunch of things on-chip.
You also get 10Kx9 onchip dual-port cache memory.

Figure 27 bits in for the video, 27 bits out.  24 Color, HS, VS, VENA. (Active video)
56 IOs.
20 outputs for your custom output pins.
+Use a dedicated clock pin for clk input. (Compiles better when using dedicated clocks for clocks and you get the use the PLL if you want.  You might consider using the dedicated PLL clk out pin also if you are passing video through the PLD) 
Total.
77 IOs going the route of additionally piping the video through the PLD, otherwise, you only need 48 IOs.

You can select different output voltage standards for different banks of IOs, like 3.3v, 2.5v, 1.8v, 1.2v.

IE, 1/4 of the PLD can be powered to 1.8v IOs while the rest is 3.3v IOs.
5v for these larger PLD and FPGAs is rare today.

[BrianHG]

Also note that the 10M04SCE144C8G is double the logic and double the cache ram size of the 10M02SCE144C8G for only a few dollars more while 10M08SAE144C8G is 4x the logic and 4x the cache ram, but around triple the price at around 21$.  144 pin drop in replacements exist up to 20x the size of the smallest one.

But still, they are all 144 pin drop in replacements.

[james_s]

Don't you think you should write the code and get it working before you settle firmly on the device to use?

[BrianHG]

Don't you think you should write the code and get it working before you settle firmly on the device to use?

Excellent point.................................

[xaxaxa]

Also note that the 10M04SCE144C8G is double the logic and double the cache ram size of the 10M02SCE144C8G for only a few dollars more while 10M08SAE144C8G is 4x the logic and 4x the cache ram, but around triple the price at around 21$.  144 pin drop in replacements exist up to 20x the size of the smallest one.

But still, they are all 144 pin drop in replacements.

If an additional 1.2V buck converter isn't a problem I'd recommend xc6slx9, also in a tqfp144 package but bigger (9K logic elements) and cheaper ($5 on aliexpress). An spi flash chip costs pennies and you only need to wire it up to the fpga (no additional circuitry needed).

[asmi]

If an additional 1.2V buck converter isn't a problem I'd recommend xc6slx9, also in a tqfp144 package but bigger (9K logic elements) and cheaper ($5 on aliexpress). An spi flash chip costs pennies and you only need to wire it up to the fpga (no additional circuitry needed).

I would NOT recommend it because it's already the largest part in that package, while MAX10 has full density range in that package.
I don't understand why everyone is so afraid of BGAs? In many ways they are easier to work with than, for example, QFNs. As a matter of fact, if the device is available in BGA and some other package, I prefer BGA (as long as it's pitch is not too small).

[james_s]

I'm not afraid of BGAs, but I tend to avoid them for my projects because it drives up the cost of the boards, you pretty much need 4 layers minimum.

It's all academic here anyway though, for a project like this using a large FPGA is like using a sledge hammer to drive a finishing nail.

[asmi]

I'm not afraid of BGAs, but I tend to avoid them for my projects because it drives up the cost of the boards, you pretty much need 4 layers minimum.

For most hi-speed interfaces you will need 4 layers minimum because of controlled impedance requirements. But I've noticed people are avoiding BGAs even on those boards, which is what puzzles me. I've learn to like BGA because they allow for very space-efficient routing, and they tend to me physically smaller than equivalent non-BGA packages (for example FBGA-256 has 256 pins and is 17x17 mm while TQFP-144 has only 144 pins, but is physically larger - 22x22 mm).

[asmi]

Dont disturb my comfort zone.

If you never leave your comfort zone, you will never grow as engineer.

[james_s]

Well personally I'm rarely doing anything particularly high speed. My own FPGA projects are mostly replicating 40 year old tech, 12 MHz is "fast".

[nctnico]

Hello, please help.
 

For my electronic design, I am experimenting what device will be better, FPGA or CPLD, I wish to compile and determine the amount of space this takes on a device then judge my needs. I am trying to do as per this image, I have simple task of finding right 3 byte condition in parallel data stream, coming at about 12-22 Mhz, lets say I will have about 50-100 of these 3 byte conditions. These 50-100 or so conditons will in turn, signal 20 or so different  type events ( pins). So some  event pins will work for a multitude of 3 byte conditions.

So you have 20 outputs and 24 inputs. The limit is the number of logic it needs in between to detect the input values you are looking for. I think the best approach is to write a piece of code in Verilog or VHDL (*) and then compile it for various CPLDs and if it doesn't fit an FPGA. It all depends on the number of equations needed which in turns depends on how well the values you are looking for can be combined into the least number of logic equations. It is hard to tell how much logic will be needed in advance.

The biggest difference between a CPLD and an FPGA is that a CPLD can typically run from a single 3.3V and has an internal flash. An FPGA OTOH typically needs multiple voltages and an external storage. The start-up time for an FPGA is usually longer. Also an FPGA uses more or less small chunks of logic in series depending on the complexity of the combinatorial equations so the timing is less predictable compared to a CPLD which uses large AND/OR terms.

(*) In VHDL I'd define an array with the values (per output) you are looking for and then iterate through these with a for-loop to compare with the inputs to set the output. The synthesizer will create combinatorial logic from this and it will have a clean interface for entering the combinations to detect.