CPLD or FPGA, please help

[BrianHG]

You are at a point where you should just purchase a SBC with linux installed which has a HDMI/DVI video input capture capability and write your own software for it.  It will take a fraction your time and you will get the added video out, networking, a full os, keyboard/mouse/usb and everything else which comes with a full at least dual core 1-2GHz computer with graphics accelerator for under 100$.  All components assembled on a module, including flash and ram and a flash port as well.

[lawrence11]

Too slow.... I need to modify that board.

[lawrence11]

Ok Brian,

Tell me exactly why again you say I cant use an TQFP 144?

I have some tqfp-144 with like 400000 ram bits.

We come to a wall here.

It cant be BGA.

That a no go zone.

[nctnico]

Ok Brian,

Tell me exactly why again you say I cant use an TQFP 144?

I have some tqfp-144 with like 400000 ram bits.

We come to a wall here.

It cant be BGA.

That a no go zone.

Get an FPGA + DDR memory on a module but make sure the FPGA is supported by the free version of the vendor tools.

[asmi]

The reason I prefer Xilinx chips for my projects is that it provides a good amount of IPs for free, which includes DDR1/2/3 memory controller. Altera only provides a time-limited evaluation version for free, if you want a permanent one - you will have to pay $$$. Developing DDR controller is a complex task way beyond beginners' abilities (and many non-beginners too - I personally wouldn't even think of it at this point).
But choosing Xilinx means you have to get comfortable using BGA chips because memory controller is not supported in TQFP version of Spartan-6, while all 7 series chips are BGA-only. DDR2/3 only exists in BGA packages as well. I was kind of afraid of BGAs before I actually started using them, but once I did they turned out to be much easier than I expected. Like I said above, I had more problems with QFNs than I did with BGAs so far.

[NorthGuy]

I was kind of afraid of BGAs before I actually started using them, but once I did they turned out to be much easier than I expected.

I agree. BGAs are the easiest thing to solder during prototyping. Just apply flux, place BGA and heat. Much less effort compare to TQFP.

[lawrence11]

Xilinx sounds good then, and this has seperate voltage I/O right?

I'll think about it. If this requires an oven I'm screwed,

My other solution, the easiest.

Is jsut to stay under 100million pixels per second.

And use some good old expensive 10ns sram. 3.3 volts everywhere.

Where is this "DDR+FPGA" on a module?

[james_s]

There are a number of DDR controllers out there, at least some of which should be fairly platform agnostic.

http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller

https://github.com/stffrdhrn/sdram-controller

Keep in mind that even if you have an IP core there is still usually a considerable amount of work required to integrate it. You have a very long road ahead to get this working. This is sounding orders of magnitude more complex than the goal originally described.

[mrflibble]

The reason I prefer Xilinx chips for my projects is that it provides a good
amount of IPs for free, which includes DDR1/2/3 memory controller.

Yup, same here.

Where is this "DDR+FPGA" on a module?

See this one for example: Xilinx Artix-7 35T FPGA, dual 100 MBit Ethernet transceivers, 512 MByte DDR3 SDRAM
https://shop.trenz-electronic.de/en/TE0710-02-35-2IF-Dual-fast-Ethernet-Artix-Module-with-Xilinx-Artix-7-35T-ind.-temp.-range?c=148
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Artix-7/

Trenz has a fairly wide range of fpga modules you can choose from.
And if you don't want to mouseclick waaaay over in the land of Bratwurst
and my grandfather's bicycle, you can always mouseclick closer to home:
https://www.digikey.com/en/supplier-centers/t/trenz-electronic

[amspire]

I know how SRAM works, I used it before and tested it. Its beautiful, I give it an adress, sink some pins, bingo, next address, new data.

I wanna make SDRAM appear like SRAM, and forget about it.

I haven't been following this thread, so I may be missing the obvious. Is there any reason you cannot use 3 static ram chips for a 24 byte read and write? Probably only use 16 extra I/Os compared to a single static RAM.

[asmi]

I haven't been following this thread, so I may be missing the obvious. Is there any reason you cannot use 3 static ram chips for a 24 byte read and write? Probably only use 16 extra I/Os compared to a single static RAM.

At that kind of speed you will likely need to length-match all lines to avoid timing issues. And doing that for 3 chips is not easy and I doubt you can get away with 2 layers (or even four). Typical dual x16 module DDR3 routing requires at least 6 layers.

[asmi]

Anyways, BGA looks cool, with an oven, wich I dont have, yet.

But once u got an oven...looks so nice for lazy people.

I use cheap-ass T-962 oven which I got for like $200. To give a perspective, my recent 6 layer boards order was ~$240 (that is extremely cheap, same specs order in Europe/US would be well over $1000), and a set of parts for assembling a single board is about $200. Even though some people here say this oven is crap, I use it for oven 2 years now with great success after some initial modifications to flash community firmware and some small HW changes (there are many guides out there on what to do and how to do it, it's a one-time deal which took about 3 hours for me to perform).
Another thing you will need to get comfortable with is placing very small parts. While some FPGA can be decoupled with 0402 parts, using 0201 caps makes it much easier from the layout standpoint as these parts fit perfectly between breakout vias of 1.0 mm pitch BGAs. But these are 0.6x0.3 mm parts, and you will need some kind of microscope to place them.

[NorthGuy]

Anyways, BGA looks cool, with an oven, wich I dont have, yet.

You can get by with hot air.

If money is a problem, you can buy a toaster oven in Wal-Mart for $20.

[asmi]

You can get by with hot air.

Not with double-sided parts placement which is all but required. Theoretically decoupling caps can be soldered manually, but soldering 0402 parts will drive you nuts in no time flat even with good stereo microscope and fine iron tip, while hand-soldering 0201 caps will most likely crack them by thermal shock - and MLCC caps tend to become conductors when cracked, so it will be extremely hard to find the one that failed without removing them all as DMM will just show you that there is a short circuit, but won't tell you which of 50+ caps failed
Also uneven heating might crack parts - especially physically large ones like FPGAs. I personally use hot air gun only when oven can't be used.

If money is a problem, you can buy a toaster oven in Wal-Mart for $20.

Like I said above, $200 is not that much money considering we're talking about parts with price in the same ballpark. I somehow doubt that a person who can afford spending that kind of money on parts (let's face it - there WILL be multiple respins due to layout/schematic bugs, and desoldering and reballing BGA is not always an option) is going to have issues making a one-time investment in equipment.

[lawrence11]

Ok,


I have nailed down the 2 only solutions possible for me.

My original idea, with 10ns sram and low resolution. All TQFP, all 3.3 volts. About 10$ more in components, cheaper PCB.

Or some DDR2,400mhz clock, 16 bits, WBGA package

https://www.digikey.com/products/en/integrated-circuits-ics/memory/774?k=ddr2&k=&pkeyword=ddr2&pv1291=4952&FV=8e80071%2Cmu400MHz%7C800%2Cffe00306%2C238067c&mnonly=0&ColumnSort=1000011&page=1&quantity=0&ptm=0&fid=0&pageSize=25

And this XC6SLX9-2FTG256C, Startan 6 FPGA, with the MCB hardware package

https://www.digikey.com/products/en/integrated-circuits-ics/embedded-fpgas-field-programmable-gate-array/696?k=fpga&k=&pkeyword=fpga&pv1291=5227&FV=ffe002b8%2Cffece02b&mnonly=0&ColumnSort=0&page=1&quantity=0&ptm=0&fid=0&pageSize=25

[asmi]

Or some DDR2,400mhz clock, 16 bits, WBGA package

https://www.digikey.com/products/en/integrated-circuits-ics/memory/774?k=ddr2&k=&pkeyword=ddr2&pv1291=4952&FV=8e80071%2Cmu400MHz%7C800%2Cffe00306%2C238067c&mnonly=0&ColumnSort=1000011&page=1&quantity=0&ptm=0&fid=0&pageSize=25

And this XC6SLX9-2FTG256C, Startan 6 FPGA, with the MCB hardware package

https://www.digikey.com/products/en/integrated-circuits-ics/embedded-fpgas-field-programmable-gate-array/696?k=fpga&k=&pkeyword=fpga&pv1291=5227&FV=ffe002b8%2Cffece02b&mnonly=0&ColumnSort=0&page=1&quantity=0&ptm=0&fid=0&pageSize=25

Forget DDR2 - DDR3 is better in any way possible - it's faster, has higher capacity, tighter tolerances on drivers' strength, and is even easier to route due to ability to use fly-by routing for address/control lines.
XC6SLX9 part doesn't have any GTPs so you will have to use external HDMI RX chip. If so, I'd prefer using faster Artix-7 (or Spartan-7 if your application is not going to be DSP-heavy) as Vivado IDE is much much better in my opinion than old rusty ISE.
Next, you will need to implement a wide memory bus to get the kind of bandwidth you need. I'd use dual x16 DDR3 chips, which at 400 MHz gives you 25 Gbps of peak bandwidth, which would give you plenty of headroom. And even using lowest speed grade (-1) will allow you to run memory at 333 MHz which will yield 20.8 Gbps of peak BW, so you can save some money on not investing into -2 speed grade, even though there are some design-related implications for doing that, which I won't go into here as not to overload you with all technical details.
Now, such memory controller with x32 DQ bus will consume 2 out of 4 IO banks (because it will need to be powered by 1.5V for DDR3 or 1.35V for DDR3L), and will force you to use voltage translation as the only fully routed banks on that package are ones used for configuration as well (banks 14 and 15). Depending on what else you will want to connect, you might want to opt for larger package. Especially since HDMI RX's RGB interface requires quite a number of pins as well.
Lastly, do you have any estimates on how much FPGA resources your application will consume? The flip side of 7 series memory controller's flexibility is that it will consume 10-15k LUTs all by itself, which pretty much demands 35T (talking about Artix-7 here as I'm most familiar with them) part as a minimum. If you're not sure, it's usually recommended to place the largest density part available in your package of choice on the prototype and then downsize it once you know exactly how much resources will you need, but for the love of God don't place big (and expensive) part on the very first revision of your board as chances are you're going to find some issues with schematic or layout (or both), and smoking $25 part will look much better than smoking $130 one.

[nctnico]

Vivado IDE is much much better in my opinion than old rusty ISE.

Just wondering: in what way do you think Vivado is better? Do the tools also build a design faster or is it just the user interface?

[asmi]

Just wondering: in what way do you think Vivado is better? Do the tools also build a design faster or is it just the user interface?

1. It works in Win10 Pro without nasty hacks or virtual machine.
2. Xilinx provide Microblaze softcore for free for all 7 series devices, which is not the case for S6.
3. I really like visual designer because it helps to visualize the system and how each parts of it are interconnected. Staring at HDL is nowhere near as "visual".
4. SystemVerilog support with some advanced IPs like AXI Verification (which is written entirely in SV) which makes developing testbenches for AXI-capable components MUCH easier (issuing a transaction in a testbench now takes only few lines of code).
5. "Cleaner" and IMHO more logically-organised GUI where controls are mostly where you expect to find them.
7. Most importantly it's not "abandon-ware" like ISE is.

I also like 7 series fabric because it's faster than S6. My initial detractor was BGA only package options (S7 was initially announced in TQFP-144 package, but it got cancelled somewhere along the way), but once I realized that DDR2/3 only exist in BGA packages as well, and got over my fear of them, I can now select a device based on what kind of capabilities I need for a specific project, not on what's available in packages I can work with.

[nctnico]

But it doesn't route faster? I'm using ISE primarily to drive the tools (but some are makefile projects so ISE sees even less use). I've moved editing HDL to Eclipse several years ago.

[asmi]

But it doesn't route faster? I'm using ISE primarily to drive the tools (but some are makefile projects so ISE sees even less use). I've moved editing HDL to Eclipse several years ago.

I don't know if it's faster or not because I didn't run side-by-side benchmarks. But in case of block diagram-driven designs, it can use OOC synthesis to make main process faster, so theoretically there might be some time savings.
Personally I'm not very concerned by synthesis or P&R times as my projects aren't very large as I simply can't afford big enough FPGAs for "compilation" time to become a problem

[nctnico]

Synthesis and P&R times are an issue for me. Some designs I work on take several hours on a fast machine.

[asmi]

Synthesis and P&R times are an issue for me. Some designs I work on take several hours on a fast machine.

Well technically you should be able to run the same HDL through both ISE and Vivado to see which one is faster on your setup.

[BrianHG]

Good luck on trying to get this 1 IC, then you don't need a FPGA or DDR3 ram:
http://docs-europe.electrocomponents.com/webdocs/1383/0900766b81383bf9.pdf

[james_s]

I'd be curious to see what sort of stuff takes several hours to synthesize, must be impressive. Most of my projects synthesize in under a minute.

[rstofer]

An unscientific comparison (a WAG) shows Vivado to be about half the speed of ISE.  It is absolutely grim on anything but the highest performance PCs available.  That it won't use more than 4 cores (8 threads) means there is no point in buying one of the truly outrageous Xeon systems.  I don't know if the commercial incantation runs any faster.  I only use the 'freebie'.

In the end, it doesn't matter.  ISE doesn't support the new chips and Vivado doesn't support the old ones (of which I have several boards).  It is imperative to have both versions running.

I put together a machine just for Vivado - I7-7700 and very fast Samsung 960 EVO SSD (1 TB) and I can go from text edit to device programmed in about 2 minutes for the LC3 16 bit RISC project (about 2000 lines of code).  That's a long time given my short attention span. 

The project uses very little of the Digilent Nexys 4 DDR board capability so routing isn't all that time consuming.  I suspect if I had a project that used most of the resources, it might take a very long time to route (hours and hours).  Good thing my projects are small!

Google for 'Vivado seems slow'...