CPLD XC95108 5Volt tolerant attached to CMOS Static RAM: good signal integrity?

[legacy]

hi
I am tempted to attach a CMOS Static RAM to a CPLD, say XC95108 5V tolerant.

I wonder about how good the signal integrity will go due to the strictly TTL outputs of the Static RAM.

Any experience ?

[legacy]

I wonder about VIH, if it will be good enough 

[legacy]

if you look at the IDT website for an example of Static RAM, there are IBIS models for simulation which are essentially voltage vs current curves data for I/O pads.

[Bruce Abbott]

XC95108A:
V_OH for 3.3V outputs >= 2.4V  I_OH = –4.0mA
V_OL for 3.3V outputs  <=  0.4V I_OL = 8.0mA

TTL (74LS04):
V_OH >= 2.4V I_OH = -0.4mA
V_OL <= 0.4V I_OL = 16mA
 

[nctnico]

I wonder about VIH, if it will be good enough 

The SRAM datasheet says Vih=2.2V so when driven with 3.3V logic it will be OK unless the board layout and decoupling are extremely screwed but in that case the board is likely not to work with 5V levels either. However when replacing memory in an existing system you might want to look at glitches on the write strobe. Some memories start a write cycle with a very narrow pulse while others do nothing. The first can cause mysterious memory corruption problems. The way to find it is to measure the normal write cycle length and then set a trigger for shorter write cycles with the device running for a couple of hours doing it's normal functions.

[legacy]

mysterious memory corruption problems.

Exactly what was happening. Thanks for the trick 

[legacy]

I was looking in the wrong direction. Thanks guy