Custom Lattice MachXO2 1200HC Board

[soFPG]

Hi,

I would like to re-create this A2-Board (https://www.cnx-software.com/2017/07/24/tinyfpga-is-a-breakout-board-for-lattice-semi-machxo2-fpga/) for the MachXO2 1200HC FPGA with a few extras.
One of my questions is, why the creator of the A2-Board didn't use a pull-up resistor for the JTAGENB pin? The MachXO2 Programming and Configuration Usage Guide (http://www.latticesemi.com/view_document?document_id=39085) on page 19 tells that there should be a pull-up resistor to enable the JTAG interface.

In the pages before the pin PROGRAMMN and INIT were mentioned but as it seems they don't play any role in respect to JTAG programming functionality because the A2-Board doesn't use them (here is the schematic: https://github.com/tinyfpga/TinyFPGA-A-Series/blob/master/board/TinyFPGA-A.pdf).

I am also wondering if such an amount of capacitors is necessary?

[iMo]

why the creator of the A2-Board didn't use a pull-up resistor for the JTAGENB pin?

Because the A2 board shall operate with JTAG disabled as the default mode (thus the JTAG pins are used as standard IOs).

I am also wondering if such an amount of capacitors is necessary?

The A2 board is well designed as the decoupling and routing is concerned. I would stay with the ferrite bead and all capacitors. Also do not fragment the solid bottom ground plane too much..

Capacitors and decoupling [Edited]:
==========================
1. a single capacitor cannot cover entire freq spectra!
The best practice is to use 3 capacitors in parallel, ie. 1nF || 100nF || 10uF, mind the 1:100 ratio (it is rarely done that way)

2. the 3 caps shall be placed such the 1nF is the closest to the Vcc pin, then 100nF, then 10uF

3. a good practice is to use 2 vias at the GND side of each decoupling capacitor (ie. when GND plane is at the bottom pcb side).

[soFPG]

Because the A2 board shall operate with JTAG disabled as the default mode (thus the JTAG pins are used as standard IOs).

So if I only want to use JTAG for programming it would be good advice to use this pull-up resistor on JTAGENB?

I am wondering if this Jtag programmer from china: https://www.ebay.com/itm/USB-Download-Cable-Jtag-SPI-Programmer-for-LATTICE-FPGA-CPLD-1000-2000-4000/301286854526 would do the job?

Am I right that TRST, INIT and PROG aren't used? Are the two GND pins and the one VCC pin inputs (e.g. I have to supply power) or outputs (power is supplied by those pins)?

The best practice is to use 3 capacitors in parallel, ie. 1n||100n||10u, mind the 1:100 ratio (it is rarely done that way)

Okay, then I do it that way.

This is my schematic at the moment, is there anything (horribly) wrong?

[ThomasDK]

The best practice is to use 3 capacitors in parallel, ie. 1n||100n||10u, mind the 1:100 ratio (it is rarely done that way)

Okay, then I do it that way.

This is my schematic at the moment, is there anything (horribly) wrong?

You missed the point:
Three capacitors per VCC pin! That is why it is rarely done that way, even though it is best practice.

An often used approach is to share the bigger capacitors between multiple pins.
For example 1x10uF per 4 pins, 1x100nF per 2 pins and 1n on every pin.

[iMo]

Exactly, look at the A2 board, there are maybe 6 Vcc pins decoupled with 1 or 2 caps, each Vcc/Vccio pin decoupled separately.

You may not use 3 caps per Vcc pin, I would copy the A2 (copy it 1:1 and add the 3.3volt regulator as in your schematics with the cap at its input). There is a ferrite bead in A2 as well.

You may place the pads for the JTAGENB resistor, you may not populate it when not required.

Btw: the 3 caps shall be placed such the 1n is the closest to the Vcc pin, then 100n, then 10u

PS: I did a similar DIL32 iCE40LP384 board in past, and I put 22ohm resistors in each signal line (to suppress the excessive ringing with longer cables). I would not do it again (a lot of work with soldering them in)..

Programming: the cheapo FT232H boards work with Diamond/Radiant usually, but I cannot guarantee the Mach likes them too

[soFPG]

Thanks a lot for your answers!

Programming: the cheapo FT232H boards work with Diamond/Radiant usually, but I cannot guarantee the Mach likes them too

I guess that the FT232H utilizes SPI/I²C to program the chip. The Programming and Configuration Usage Guide on page 6 claims that only JTAG offers full memory space accessibility so I would rather stick with the jtag tool.

Are FPGAs generally more sensitive in regards to capacitors? I never used 1nF caps for my µC boards and they work fine, but they all have only one VCC pin.

You may place the pads for the JTAGENB resistor, you may not populate it when not required.

Good idea, thanks!

There is a ferrite bead in A2 as well.

Okay, ahm, why do I need this? Wikipedia tells me that it is used to suppress high frequency noise but where would that noise come from?

I am sorry I don't have a lot of experience in PCB design and I don't have an electronics background but I like to design and create things myself. A few years ago I started with software development and now I want to learn more about the actual hardware.

[daveshah]

An FT232H can program a MachXO2 using JTAG too, you might need to reprogram the PID/VID, but I've always got by fine with a FTDI MPSSE cable for MachXO2 and iCE40 programming. The only gotcha is a slight timing issue I've sometimes noticed, solvable by adding a small capacitor (circa 18 or 22pF, whatever you have around) from TCK to ground.

[soFPG]

So something like this (https://www.ebay.com/itm/High-speed-CJMCU-FT232H-Multifunction-USB-to-JTAG-UART-FIFO-SPI-I2C-module/162736978843) would be appropriate? How do I re-program this chip and how would I know which pins of the ftdi-board are used for jtag?

[mikeselectricstuff]

The jtagen pin needs to be explicitly enabled in the config, to allow the jtag pins to be used as i/o, so if the jtag pins are dedicated to jtag, that pin isn't used.

[soFPG]

so if the jtag pins are dedicated to jtag, that pin isn't used.

But wouldn't the jtagen-pin allow the use of the jtag-pins as jtag-pins (and not standard I/O) by a pull-up in the first place?

[iMo]

So something like this ... would be appropriate? How do I re-program this chip and how would I know which pins of the ftdi-board are used for jtag?

That board works as a programmer under Diamond programmer with iCE40xx (SPI mode), and with the Reveal Analyzer under Radiant (JTAG). Haven't tried with Mach under Diamond but 99.9% it will work - the Diamond programmer does recognize it. The programming software sets the mode as required.

The JTAG pins are AD0-AD3 on that board, there is the datasheet from FTDI describing all the modes and pin mappings for the particular mode. Most probably there will be the JTAGENB related signal used as well, it could be one from the AD4-AD7.

PS: that board works as Serial/USB converter as well. The pins AD0 and AD1 are used. WinXX installs the driver for you automatically and you get a COMxx port available.

[mikeselectricstuff]

so if the jtag pins are dedicated to jtag, that pin isn't used.

But wouldn't the jtagen-pin allow the use of the jtag-pins as jtag-pins (and not standard I/O) by a pull-up in the first place?

It's a configuration setting in the flash. In the default factory state, JTAG pins are always JTAG and JTAGEN has no effect.
If you then enable JTAGEN in the configuration data, the JTAGEN pin muxes the JTAG pins between JTAG and I/O

[iMo]

Okay, ahm, why do I need this? Wikipedia tells me that it is used to suppress high frequency noise but where would that noise come from?

The noise comes from the Mach FPGA. The ferrite bead suppresses EMI which may spread out (off the Vcc power rail).
Also it suppresses the noise coming into your board from your power supply or other modules/boards..
The FPGAs are pretty fast devices creating EMI up to GHz.

PS: do not use "inductor" rated in uHenrys. Use "ferrite bead" rated in ohms (30-50ohm is ok). In ohms as it indicates a broadband impedance.

[soFPG]

Is this good enough?

I am wondering how the designer of the A1 board did the pcb layout, especially at that size. Seems almost impossible to me to do it as clean as he did.

[iMo]

The ferrite bead is not wired properly.
You have to create ie. "3.3E" (External- wired to your pin headers) and the internal "3.3V".
The FB has to be wired in between. See an example below..

PS: why the 5V at the JTAG header? The Mach is 3.3V io chip..

[soFPG]

You have to create ie. "3.3E" (External- wired to your pin headers) and the internal "3.3V".

I use external 5.0V, those will be converted to 3.3V by the voltage regulator.

why the 5V at the JTAG header? The Mach is 3.3V io chip..

I would like to have the JTAG connector and the 5.0V and GND input in the same place later on my PCB layout.

Like this:

[iMo]

You have to create ie. "3.3E" (External- wired to your pin headers) and the internal "3.3V".

I use external 5.0V, those will be converted to 3.3V by the voltage regulator.

Have a look at the schematics with 3.3E and 3.3V above.
We talk about the 3.3V rail which has to be split into 3.3E and 3.3V (and FB in between).

[soFPG]

Oh, okay my bad, I missunderstood.

So the ferrite bead suppresses high frequency noise from the voltage regulator?

[iMo]

The FB helps with suppressing the HF noise:
1. from Mach to 3.3E pin headers (and to following external circuitry)
2. from 3.3E pin headers to Mach (from the external circuitry).
Mind there are 3.3V and 3.3E rails in my schematics above.

[soFPG]

Today all parts came together (FPGA, Board, resistors etc.), so I soldered the board.

You may blame me for not using a ferrite bead but I consulted a person with phd in electrical engineering and it seems ferrite beads are mostly used to keep high frequency radiation low to pass specific test, not to keep the device functional.

Yeah, but somehow my board isn't working

Instead of 4.7kOhms I had to use 2.7kOhms I had lying around because the chinese seller delivered 100Ohm instead of the ordered 4.7k, but I think that won't make a significant difference? 

I downloaded Lattice Diamond, created a short VHDL file which just turns Pin 17 on, flashed my FT232H to a Lattice USB JTAG device (which gets recognized by Lattice Diamond):

Code: [Select]

INFO - Cable Auto Detection Activated.

INFO - No Lattice HW-DLN-3C (parallel) cable detected.

INFO - No Lattice HW-USBN-2A cable detected.

INFO - Board with FTDI USB Host Chip detected.

INFO - Detected HW-USBN-2B (FTDI) cable at port FTUSB-0.

but if I try to upload the code to the FPGA I get this error message:

Code: [Select]

Starting: "pgr_project save "D:/Programme/Lattice Diamond/Projects/Proj1/impl1/impl1.xcf""

Starting: "pgr_program run"

INFO - Check configuration setup: Start.

Device#1 LCMXO2-1200HC: Failed to verify the ID
(Expected: 0x012BA043 Read: 0xFFFFFFFF).

ERROR - Check configuration setup: Unsuccessful.

ERROR: pgr_program failed.

ERROR - Programming failed.

I use pins ADBUS0 - ADBUS3 (TCK, TDI, TDO, TMS) from FT232H. I also attached the config file.

I attached my schematic and routing. Could this really not be working just because of a missing ferrite bead?


Edit: I just took a look in the FT232H data sheet (Page 9 : http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf). The template file for the Lattice Programmer uses 245 FIFO-Mode instead of Serial RS232.
Which pins are responsible for JTAG in this mode? Instead of TCK/TDI etc. they are now called D0, D1, ..., RXF, TXE,RD. Which do I have to use?

[SiliconWizard]

I still don't know why you put 5V on the jtag connector. (It could be unsafe if you ever use this voltage pin to get the voltage reference for a standard JTAG adapter.)

As others have said, pulling up JTAGENB is optional if you don't intend to use this functionality (JTAG disable, which must be programmed).

Also, your FTDI programming file (XML) specifies a VID of 6010 and a port B - this file is just for a FT2232H and not a FT232H! You have managed to fool Lattice Diamond which "detects" it, but fooling FTDI's own libraries will be a little more difficult.

The correct VID for the FT232H is 6014 and it only has port A. The FT232H does support JTAG *but* the FTDI JTAG library only seems to support FT2232H and FT4232H chips - not the FT232H, and most likely, Lattice has used FTDI's library (which seems confirmed by the presence of the file 'ftcjtag.dll' among Lattice executables). (See: http://www.ftdichip.com/Support/SoftwareExamples/MPSSE/FTCJTAG.htm )

So if you're not using an FT2232H, you may be out of luck. I have an FT2232H-based adapter and it does work. Never tried with an FT232H. But I suspect it won't work.
Since FTDI provides the source code for the FTCJTAG library, you may be able to modify it to be able to support the FT232H, rebuild the DLL and replace the original one. Good luck!
(Buying an FT2232H module will certainly be much less hassle.)

[iMo]

The fact the device ID has not been recognized does not necessarily mean the FT232H cannot program it.
I use the FT232H with Diamond Programer in SPI mode for iCE stuff and with Radiant Analyzer in JTAG mode.
The FT232H is properly detected

Code: [Select]

INFO - Detected HW-USBN-2B (FTDI) cable at port FTUSB-0.now you have to learn how to connect it to your board. There could be a dozen of reasons it does not work straight with your new board.
This indicates wiring issues:

Code: [Select]

(Expected: 0x012BA043 Read: 0xFFFFFFFF)Double check the wiring and read the tutorials. The Mach02 is using JTAG for programming so it will work.
I would definitely not start to mess with USB vids and xml config files 
Here is the FT232H wiring for the jtag (from the FT232H datasheet):

 

[soFPG]

I still don't know why you put 5V on the jtag connector. (It could be unsafe if you ever use this voltage pin to get the voltage reference for a standard JTAG adapter.)

This is not part of the JTAG-connector. I use loose wires for connection. The 5V and GND pins are powering the whole board.

As others have said, pulling up JTAGENB is optional if you don't intend to use this functionality (JTAG disable, which must be programmed).

But as far as I understand, the Mach XO2 is programmed via JTAG - so how would disabling JTAG functionality be beneficial?

Also, your FTDI programming file (XML) specifies a VID of 6010 and a port B - this file is just for a FT2232H and not a FT232H!

But as you can also see - it defines a Port A as well! Maybe I have to remove Port B to get it working...I think only one port is needed? FT232H has one MPSSE unit, FT2232H has two (as far as I know).

Double check the wiring

What I did:

ADBUS0 - TCK
ADBUS1 - TDI
ADBUS2 - TDO
ADBUS3 - TMS

I don't know why they are called D0-D7 in 245 FIFO-Mode though.

in JTAG mode with radiant analyzer.

So it should work with MachXO2 FPGAs and Diamond as well?

I would definitely not start to mess with USB vids and xml config files

What do you mean? Without any E²PROM flashing Lattice Diamond didn't recognize the FTDI chip as a valid programming tool. So I guess that procedure was mandatory.

[iMo]

Without any E²PROM flashing Lattice Diamond didn't recognize the FTDI chip as a valid programming tool.

Never heard about.. That procedure is definately not mandatory. Take the FT232H and use it. That is all. Diamond has recognized it as channel 0 of the FT2232.
Read above post from daveshah.
PS: I've attached above the table with FT232H jtag wiring..

[soFPG]

Read above post from daveshah.

So which PID/VID should I use? 

PS: I've attached above the table with FT232H jtag wiring..

Thanks for your help - I connected the pins as I wrote in my last post.

Edit: I just completely erased the EEPROM of my FT232H and Lattice Diamond still detects a "HW-USBN-2B (FTDI)" cable at port "FTUSB-0"  (But still same error message)