custom little SoftCores, what do you think about this? [closed]

[legacy]

Code: [Select]


 * Instruction format:
 *
 *   17  16  15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 0 | 0 |   operation   |      dst      |              imm              | - alu imm
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 0 | 1 | smode | dmode |      dst      |      src      |     offset    | - mov
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 1 | 0 |   operation   |      dst      |      src      |    reserved   | - alu
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 1 | 1 | 0 | 0 |                     must be zero                      | - ret
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 1 | 1 | 0 | 1 |                        address                        | - call
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 1 | 1 | 1 | 0 |                        address                        | - jump
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 1 | 1 | 1 | 1 |    cond   |                     rel                   | - branch
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *


Code: [Select]

* 'operation' can be one of the following:
 *
 *  two cycle operations (00--)
 *
 *  0000 logical shift right
 *  0001 logical shift left
 *  0010 multiply
 *  0011 -- reserved
 *
 *  single cycle operations
 *
 *  0100 bitwise and
 *  0101 bitwise or
 *  0110 bitwise xor
 *  0111 -- reserved
 *  1000 bitwise invert
 *  1001 memory load
 *  1010 move
 *  1011 byte swap
 *  1100 add
 *  1101 -- reserved
 *  1110 subtract
 *  1111 compare
 *
 *  smode/dmode can be one of the following:
 *
 *  00 direct register load/store ("mov reg, reg" not supported)
 *  01 indirect load/store (offset is added to base address)
 *  02 indirect load/store with pre-decrement
 *  03 indirect load/store with post-increment
 * 
 *  branch cond codes:
 *
 *  000 BEQ
 *  001 BNE
 *  010 BCS
 *  011 BCC
 *  100 BMI
 *  101 BPL
 *  110 BLT (signed less than)
 *  111 BGE (signed greater or equal)


[rstofer]

I would take a look at the requirements for porting the GCC compiler or read through "A Retargetable C Compiler" and see what the code generator wants/needs.  One way or the other, I would want to support C from day one.  GCC would be nice because other languages should use the same backend.  If you were a real glutton for punishment, you could port the Ada runtime.

https://www.amazon.com/Retargetable-Compiler-Design-Implementation/dp/0805316701

[ataradov]

Arrangement of bits in the opcode makes no difference whatsoever. If there is no C compiler for the core, then it is pretty useless given that alternatives exist.

[C]

Code: [Select]


 * Instruction format:
 *
 *   17  16  15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 0 | 0 |   operation   |      dst      |              imm              | - alu imm
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 0 | 1 | smode | dmode |      dst      |      src      |     offset    | - mov
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 1 | 0 |   operation   |      dst      |      src      |    reserved   | - alu
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 1 | 1 | 0 | 0 |                     must be zero                      | - ret
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 1 | 1 | 0 | 1 |                        address                        | - call
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 1 | 1 | 1 | 0 |                        address                        | - jump
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *  | 1 | 1 | 1 | 1 |    cond   |                     rel                   | - branch
 *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 *


Think if you do some row swaps things will get easer.
Example, If you put "- branch" where "- call" is then you have a bit to say "address" used here.


Might be a swap for first three to make logic easer.

[legacy]

I would take a look at the requirements for porting the GCC

gcc = crap

[legacy]

Arrangement of bits in the opcode makes no difference whatsoever. If there is no C compiler for the core, then it is pretty useless given that alternatives exist.

with HC11 you usually don't need any C compiler, instead you prefer use assembly
with PicoBlaze (by Xilinx) it's the almost the same case,
and every C compiler I have seen  ... was not confortable at all (frankly the suck)

those things like the ISA above are usesable with fpga,
and usually you want to use them because you need something
easy to be implemented with a good code density

[ale500]

With 18-Bits opcodes, he is targetting FPGA's Block RAMs(but not MAX 10 directly), meaning not that much RAM. Of course Unix v 7 ran in 256 kBytes and a Cyclone V even the smallest one has > 160 kBytes.
How much addressing space are you planning ? With 14 bits for addresses, meaning 16 kWords, one can do something.... are DATA/Program spaces separated ?
CALL and RET are problematic instructions due to the stack manipulation. A link register that not always has to be pushed/popped simplifies the design. Small constants are used the most. Look at instructions statistics to know where to put the money, so to say.

Great would be if one could do a 32-bit core in say 500 LEs... in 3000 you can do almost anything.... . RISC 5 (the one used by Project Oberon) is really small for a 32-bit core: 1930 LEs (Lattice MachXO2) with floating point !, yeah those are 32 bit opcodes, though.

(But... the point about C is valid. Maybe GCC is not the best but the question is how are you planning on programming your core ? what do you want to do with it ? and others ?)

[legacy]

Think if you do some row swaps things will get easer.
Example, If you put "- branch" where "- call" is then you have a bit to say "address" used here.


Might be a swap for first three to make logic easer.

first answer about the ISA 
and it's very interesting, thanks, good idea 

[legacy]

don't worry about the tool,  I am pretty able to implement (already done)
a working assembly compiler in a couple of days during the weekend

Maybe GCC is not the best

so cool when you don't use it, gcc is for sure the worst choice 
even the dude who made the home brew cpu magic1 stayed away
and used lcc

But... the point about C is valid

If I had came in the need of C compiler for complex things like porting an OS, I would have ignored gcc
and I would have used a common architecture, such as MIPS or ARM, which all come with professional
toolchains (Keils?) and debuggers 

what do you want to do with it ?

I have implemented a debug-enine in vhdl, it's a big finite state machines which talks over the serial line
it's used to import/export things like CPU registers, signals (events like break points/watch point events)
and blocks of memory from/to the host to/from the fpga

I started this project in 2008, done in spare time, and it was used along with my own soft core Arise-v2
whose ISA is much more complex than the ISA published above

my Arise-v2 soft core hasn't yet come with an high level language such as a C compiler
I am digging in the possibility of a) retargeting lcc, or b) making my own compiler

I have an old project about that, it's a sort of "--C", just statements, labels, loops, variables and nothing else
it generated good machine code, in three passes, there is no standard linker (I am using my own symbol table format),
but it compiles module per module, and at the end there is a linking stage, even it there is no linker-script

it was done when I was a student as "examination test", useful to get my degree

anyhow, Arise-v2 is made for fun, I have a degree in computer science, I have studied "languages" and "architectures"
Arise-v2 is just "Putting Knowledge into Practice"(1), whereas the above small ISA comes for the need of having a small core
in fpga, for same need you might have for things like picoBlaze


(1) I have a job in avionics, nobody pays you to do the above things
there is no research in the direction of soft core and languages
we use ADA and Misra-C with PowerPC, and our fpgas come in the need
of getting the most out of things like ARINC 429 

[legacy]

How much addressing space are you planning ?
With 14 bits for addresses, meaning 16 kWords, one can do something....
are DATA/Program spaces separated ?

yes, no more than 14bit
data and code are separated due to implementation constrains
but you can access the code space through a trick (dual port ram)



p.s. within 512 byte I have implemented a PSX-Pad controller
on 68HC11, which happens to have (in single chip mode) 512byte of ram
including data, code, and stack
I can't,  (edit: well it's much more difficult to) achieve such a purpose in C
I'd better use assembly

[C]

Did you intend to leave out ADD & SUB with carry?
With you can do large math.

In your compiler thinking.
For pascal with modules, you hear the the "System" module is built in.

Think of this a different way. The System module was compiled separately just like any other module. The compiler then before each compile adds a line and processes it before your code "Uses System"
This causes a Read the interface which put's system in the AST and dymanic link compiler to system blob or have system blob prelinked.

This simple idea lets you remove a lot from pascal compiler and put it into the system module and still act like what is now in system module is built into the compiler.

Bit = 0..1
Byte = 0..255
SByte = -127..128
The above being in system module adds pascal's built in types using the compiler.
Go a step further a where the compiler knows how to add functions that look like operators and the compiler just got simpler again while using what has to be in compiler.
Think the current extreme is C# with Net frame work.

[legacy]

did you intend to leave out ADD & SUB with carry?
With you can do large math.

mmm, although architectures like MIPS have already shown that you can do
*carry and overflow checks* in software (e.g. the first R2K did it in that way)
I am tempted to introduce them in hardware, along with bit-fields instructions

bit{set,clear,get}

The System module was compiled separately just like any other module.
The compiler then before each compile adds a line and processes it before your code "Uses System"
This causes a Read the interface which put's system in the AST and dymanic link compiler
to system blob or have system blob prelinked.

This simple idea lets you remove a lot from pascal compiler
and put it into the system module and still act like what is now in system module is built into the compiler.

interesting, thanks 

[C]

You may have missed what I was saying
with ADD with carry

very Large number math even a small processor, when you have ADD & ADD with carry. I do not remember a CPU with out this.

in binary A, B,D = array of bits.  for crazy say 1024 bits
For an 8-bit machine this is three 128 byte arrays.

Code: [Select]

A[0] = add B[0], C[0]
for x = 1 to 127
 A[x] = ADD with carry  B[x], C[x]
next x
This is a 1024 bit add. Just changing array size and x max lets you have any size of binary add.
The first ADD sets status bit as needed for overflow of first 8 bits.
ADD with carry uses overflow bit as third input to adder and sets status bit for overflow.

The PDP11-35 was built around 4 74181 chips for math & logic. Might want to look at what 74181 does vs what you have.
http://www.ti.com/lit/ds/symlink/sn54ls181.pdf\
Note that PDP11-35 used microcode to reduce logic in CPU. While a programmer sees 8 registers, internal there were more. If memory serves 16 total.
Address buss out
data buss in
data buss out
instruction
Think there was Interrupt vector in and Interrupt level.
and some temps to reduce logic.
For a clock it used different taps from a delay line to adjust for logic path delays. It actually stopped dead for memory. A nano sec change in memory speed changed how fast the CPU ran. Accessing non existing memory caused a timeout interrupt to restart CPU in this case.

Edit: forgot the Instruction register in list.

[bingo600]

I would take a look at the requirements for porting the GCC

gcc = crap

But free

/Bingo

[ataradov]

gcc = crap

Your personal bad experience with GCC is irrelevant here. You don't support it (or any other C compiler) == your project is one of the 1000 other student cores that get abandoned the moment you get bored with it.

Now, if I needed a soft core and for whatever reason I did not like NIOS II or MicroBlaze, then I would just take basic MIPS core and be done. Even if I did not want to look around for a reasonably licensed implementation,  I can roll my own in a couple days. And I do get both assembler and C support, if I need it.

Let's say this core is to compete with PicoBlaze, then it is too wasteful.  [next statement is retracted - did not notice 18 bit opcodes at first] You have 28 bits for jumps and calls. What is the point of this? Do you really want to write a  program that big in assembly?

I simply don't see the point of why this is better than any of the existing alternatives, except that alternatives are not made by you.

[ataradov]

easy to be implemented with a good code density

32-bit instructions and good code density? Not happening. Look at Thumb-2. It is plenty for controller-like use and actually does provide density.

I feel like this is not very well positioned product. On one hand you are talking about simplicity, and on the other propose real heavy-weight architecture.

For a really embedded controller, I would like to see what interface you propose for interfacing with FPGA internals. I hope it is not full-blown AHB-like bus, that will put this thing into MicroBlaze / NIOS II / MIPS category, for sure.

[legacy]

I do not remember a CPU with out this.

dude, MIPS doesn't have it

[legacy]

32-bit instructions and good code density?

68K is 32bit, good code density

[legacy]

I simply don't see the point of why this is better than any of the existing alternatives, except that alternatives are not made by you.

PicoBlaze needs the Copyright by Xilinx, just to say

[legacy]

But free

LLVM and LCC are also OpenSource
better code, easier to be retargeted

[bingo600]

I simply don't see the point of why this is better than any of the existing alternatives, except that alternatives are not made by you.

PicoBlaze needs the Copyright by Xilinx, just to say

Well .... 

From
https://en.wikipedia.org/wiki/PicoBlaze


BSD license
http://bleyer.org/pacoblaze/

Apache license
https://github.com/krabo0om/pauloBlaze

/Bingo

[bingo600]

But free

LLVM and LCC are also OpenSource
better code, easier to be retargeted

And that makes gcc=crap ??

/Bingo

[legacy]

You don't support it (or any other C compiler)

are you really sure ? 

I did, for HPPA/PA2, when I tested gcc in the v4.1.* era
I remember when I found bugs(1), sent emails etc etc

frankly, it was when I discovered that gcc is all crap
and my conclusion is that supporting GCC or GNU
subtracts effort to other projects (e.g. to LLVM)

also, GNU has the effect of making UNUX broken
e.g. the GNU "tar" adds a lot of entropy and it's not compatible
with anything in the UNIX world (e.g. with IRIX)

you might be shocked when you see a tape's content completly distroyed
becasue the tarbal was done with UNUX tar, and GNU tar has "improved"

it's not irrelevant, I guess 

(1) one of those was interesting, since it had made the "conditional branch"
like the randomly launch of the coin, where you have the 50% of probability
to take the correct branch, and the 50% of probability to cause a crash
it happened under the -O2 flags, and … we got a disaster in Catalyst
(gentoo builder, stage1: consistently bad in quality, not able to be trusted)

[ataradov]

frankly, it was when I discovered that gcc is all crap

I'm not saying that GCC is beautiful on the inside. I agree that Clang/LLVM is way better. But it also consistently generates lower performing code. This will change of course, but that the moment is the fact.

It is like complaining about x86. Yes, it is complicated and bloated, but it is also the highest performance thing we have and we need to live with that, not just close our eyes because we don't like it.

You can bash GNU all you like, but the fact is, they have working tools, you have lots cool proposals on forums.

[ataradov]

gcc (does it stand for Get Computer Crap?) is itself crap 

If we want to have discussion at that level, then your architecture is also crap.