Cyclone FPGA and DQ pins vs general purpose IO pins

[Miyuki]

Hi
maybe it is question more to Altera forum but try it here

Im trying to figure out if is any real hardware difference between DQ pins and general purpose IO pins on Cylone devices (older ones II and III) as all DDR registers input and output are implemented in normal LEs and in handbook isn't described any feature who is just on DQ pins 
Do I miss something or are they just same ?

[Scrts]

You have to use those pins if you are implementing DDR, DDR2 or DDR3 memory controller. They're dedicated for that purpose. SDRAM and SRAM can use any pins.

[BrianHG]

You can use any IO pins for any memory, however, the DQ pins have a fast latch enable, and were designed to take 2 sets of D latches at 180 degree phase, plus then 1 third set to parallel the data so the x bits IO becomes 2x bits at the half clock speed, everything time 2 for the output direction as well.  The DQ pins in each bank also have a faster grouped output enable to swap IO direction as fast as possible + a dedicated high speed input Data Latch enable for recieving that extra 1/2 less clock cycle on data reads.

Once again, Quartus wont care is you use any IO, however, you get a F-Max and DDR speed penalty which is described in the IO memory interface section of each Cyclone type data sheet.  I've successfully made a DDR system extra wide data system a few years ago on a EP3C55-480 pin bga, using all the IOs on the faster top and bottom banks, reserved the PLL differential outputs to clock the SODIMM modules, but had a limited 165Mhz, or, 333mhz DDR instead of the top 200/400mhz the chip was capable of.  I'm sure it might have worked faster, but I would violate setup times and chance memory errors, but, I had 256 bit DDR memory instead of the maximum recommended 192 bit as per available dedicated DQ io pins.  The end result was I was still getting a little better performance due to the wider 256 instead of 1 sodim which would have been a 128 bit system at 200mhz.

[Scrts]

I had errors when assigning non DQ pins when memory controller is instantiated. I know that it's possible to play around Quartus, but it's really not straight forward. I always run pin assignment compilation prior to releasing PCB.

[BrianHG]

Yes, using Altera's DDR SDR controller, or using the external latch enable for specific DQ pin groups is crucial and you are limited by altera's controller.  Unless you know every option inside and out, like to set a fixed RDQ clock cycles for your ram module instead on relying on the external latch enable (DQS - or DQ Strobe) for every data 4-8 bits, or unless you made your own ram controller, Stick to altera's recommended pin groups unless you really know what you are doing.