DAC - Sam D21 Bare Code Driver

[Franc]

Hi friends!

I am starting to use the DAC of Sam D21 .

I would like to code it in Bare Metal.

Anyone has an example driver configuration to me study together DS? I have some doubts to coding it.

Best Regards

[ataradov]

What you've got so far and what does not work?

[rstofer]

Why not start with the App Note?

http://www.atmel.com/Images/Atmel-42110-SAM0-Digital-to-Analog-(DAC)-Driver_Application%20Note_AT03244.pdf

[ataradov]

Why not start with the App Note?

The question is about bare-metal implementation and this AN can't be any further away from that.

[Franc]

Hi RSTOFER, yes I checked that file but all information is in ASF. I do not like ASF  .

I searched a lot the driver configuration in Bare Code like that ASF file shows but no success for Bare Code.

Dear Alex, I cannot understand how I can do the syncronization for write data to DATA.reg.


Regards

[ataradov]

Dear Alex, I cannot understand how I can do the syncronization for write data to DATA.reg.

Don't think about synchronization. It is not going to affect you in this case.

[Franc]

Alex, in page 934 of DS means:

'The following bits need synchronization when written:
• Software Reset bit in the Control A register (CTRLA.SWRST)
• Enable bit in the Control A register (CTRLA.ENABLE)
• All bits in the Data register (DATA)
• All bits in the Data Buffer register (DATABUF)

so, the STATUS.SYNCBUSY is not relevant?

Thanks friend!!!

[ataradov]

so, the STATUS.SYNCBUSY is not relevant?

Synchronization is needed if you are worried about interrupt latency (within a few clock cycles). If you do two writes in a row into the registers that need synchronization, then the second write will block the system bus until the first one completes. If you only write DATA register once in a while, then you have noting to worry about.

At the same time, it is not that hard to do the synchronization. Just do something like

Code: [Select]

  while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY);
before the write to the DATA register.

[Franc]

When I debug my code with the dac_carga_init() in main.C, my program blocks.
I have configured my DAC drive as below. I dont know what happens dear Alex.

Code: [Select]

#include "samd21.h"
#include "board_defs.h"


void dac_carga_init(void)
{
PM->APBCMASK.reg |= PM_APBCMASK_DAC; // Enable peripheral clock for DAC
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID (DAC_GCLK_ID) | // DAC share same GCLK
GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN (DAC_GCLK_SOURCE);
while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN); // Wait till enabled

GPIO_dirOut(DAC_OUT); //PA02
GPIO_pmuxen(DAC_OUT, DAC_OUT_PMUX); //PMUX B for PA02 pin DAC

DAC->CTRLA.reg &= ~(DAC_CTRLA_ENABLE); //Disable DAC to permit change CTRLA B register.
DAC->CTRLB.reg |= DAC_CTRLB_EOEN | DAC_CTRLB_REFSEL_AVCC; //Enable the DAC output on Vout pin. Enable VDDANAL REF. 
DAC->CTRLA.reg |= DAC_CTRLA_ENABLE; //Enable DAC
}
.h file:

Code: [Select]

#ifndef DAC_CARGA_H_
#define DAC_CARGA_H_

void dac_carga_init(void);

inline uint16_t dac_carga_write(uint16_t carga);

uint16_t dac_carga_write(uint16_t carga)
{
// uint16_t received_data;
while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY); // Make sure clock synchronization
DAC->DATA.reg = (carga); // Write DAC value

}


#endif


Best Regards friends!

[ataradov]

Here is a full source code that works. If you want to test this as is, you can replace main.c here https://github.com/ataradov/mcu-starter-projects/tree/master/samd21 with this code.

You can go fancy with synchronization and stuff, but as I said, it is not necessary in most cases.

Code: [Select]

//-----------------------------------------------------------------------------
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "samd21.h"
#include "hal_gpio.h"

//-----------------------------------------------------------------------------
HAL_GPIO_PIN(DAC,      A, 2)

//-----------------------------------------------------------------------------
static void sys_init(void)
{
  // Switch to 8MHz clock (disable prescaler)
  SYSCTRL->OSC8M.bit.PRESC = 0;
}

//-----------------------------------------------------------------------------
static void dac_init(void)
{
  HAL_GPIO_DAC_out();
  HAL_GPIO_DAC_pmuxen(PORT_PMUX_PMUXE_B_Val);

  PM->APBCMASK.reg |= PM_APBCMASK_DAC;

  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(DAC_GCLK_ID) |
    GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(0);

  DAC->CTRLA.reg = DAC_CTRLA_SWRST;
  while (DAC->CTRLA.reg & DAC_CTRLA_SWRST);

  DAC->CTRLB.reg = DAC_CTRLB_EOEN | DAC_CTRLB_REFSEL_AVCC;
  DAC->CTRLA.reg = DAC_CTRLA_ENABLE;
}

//-----------------------------------------------------------------------------
static void dac_write(uint16_t value)
{
  DAC->DATA.reg = value;
}

//-----------------------------------------------------------------------------
int main(void)
{
  int dac_out = 0;

  sys_init();
  dac_init();

  while (1)
  {
    dac_write(dac_out++);
  }

  return 0;
}


[Franc]

In page 33 of DS SAMD21 says that PA02 is the only pin for Vout of DAC. Is possible I use any other Analog pin for do it once all are MUX B?
(PA02 til PA07 and PB00 till PB09)

Thanks!

[ataradov]

Is possible I use any other Analog pin for do it once all are MUX B?

I don't understand the question.

[Franc]

Sorry,... Could I use  any other Analog Pin to DAC Vout? In DS, page 33, shows only PA02 as Vout, but I am using the PA02 with my OLED Xplained Pro in EXT03.

[ataradov]

No, the table "Table 6-1. PORT Function Multiplexing" lists all possible multiplexing options. If it is not in the table, it is impossible. In case of DAC, only PA2 is possible.

[Franc]

Still blocking my program when I call the dac_carga_init().
I am using the SERCOM5 SPI in same EXT03.

Also in my program I am using the TCC0 TC4 TC5, SERCOM0 SPI in EXT1.

My GCLK(0) is DFLL 48Mhz. Do you know if there is any incompatibility to use them together DAC?

Below my dac_carga_init():

Code: [Select]

void dac_carga_init(void)
{
GPIO_dirOut(DAC_OUT); //PA02
GPIO_pmuxen(DAC_OUT, DAC_OUT_PMUX); //PMUX B for PA02 pin DAC

PM->APBCMASK.reg |= PM_APBCMASK_DAC; // Enable peripheral clock for DAC
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID (DAC_GCLK_ID) | // DAC share same GCLK
GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN (0);
while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN); // Wait till enabled

DAC->CTRLA.reg = DAC_CTRLA_SWRST;
while (DAC->CTRLA.reg & DAC_CTRLA_SWRST);

DAC->CTRLB.reg = DAC_CTRLB_EOEN | DAC_CTRLB_REFSEL_AVCC; //Enable the DAC output on Vout pin. Enable VDDANAL REF. 
DAC->CTRLA.reg = DAC_CTRLA_ENABLE; //Enable DAC
while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY);//Wait until clock ok.
}

Best Regards

[ataradov]

Code: [Select]

while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN); // Wait till enabled


I'm pretty sure this is wrong. And the whole line is unnecessary.

[Franc]

  ..You are the guy..Alex! Worked perfect. Thanks.

By the way.... why this line is wrong? ' while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN); // Wait till enabled'
I have used it to all my TC and no issues.

Regards!

[ataradov]

If you really want to wait until the clock is enabled, then it should be "while (0==(GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN));". Your TC is probably clocked from a slower clock, so it takes a few cycles for it to enable, so it was falling though on the first iteration.

In general, it probably is a good practice to wait, but in reality, even if clock is not enabled, your first access to the peripheral register will block until clock is enabled.

[Franc]

OK, nice clue!
*Now I will start in Analog Comparators of Sam D21.

Best Regards!