DE0-Nano - Useful bits.

[Crazy Ape]

I've seen that a few people on the forum have DE0-Nano FPGA dev boards, though not a lot of activity involving them. I have one myself but it's been sitting on the shelf since I bought it. I recall a few times where I've thought "Hmm, must look at that thing one of theses days", but beyond the thought, it remained snug in it's box on the shelf, until now..........

Well, I'm really not interested in blinking LEDs or whatever the usual familiarization process is, I want VGA, much more interesting to toy about with. Since I had to add VGA, I thought I'd document it for those looking at doing the same thing, and make it my first "DE0-Nano - Useful Bits" post, the plan is to add more in future.




How to easily add VGA & PS2 ports to the DE0-Nano for under $10


Items Required:

VGA/PS2 Module (see bellow for sources)
40 Way IDE cable (from an old PC)

This is the module (cheapest I could find):
http://www.aliexpress.com/item/VGA-to-VGA-module-PS2-PS2-module-module-test-module-adapter-board-development-board/1182820977.html

Lots there from other sellers though:
http://www.aliexpress.com/premium/VGA-module-PS2.html?g=y&needQuery=n&SearchText=VGA%2Bmodule%2BPS2&CatId=0&initiative_id=SB_20131006095829&SortType=price_asc


With a simple modified IDE cable, the module will plug straight in, I've used a piece of paper in the pictures to help with visualization.

Step 1:
First you need to separate certain groups of wires from each other, do this from the non-striped side of the cable by counting off the following groups of wires (you only need to separate an inch or two). Details in Picture 1.

Count off 10 wires, separate that group.
Count off 2 wires, separate that group.
Count off 4 wires, separate that group.
Count off another 4 wires and separate that group.


Step 2:
Cut the wires as seen in Picture 2.


Step 3:
Split and strip the two wire pair coming from the DE0-Nano Side, the top wire of the pair is 3.3v, the bottom wire is ground.
Split the group of four wires coming from the VGA module side of the cable into two pairs,  strip and twist the conductors in each pair.
See Picture 3 for more detail.


Step 4:
Solder the top wire from the DE0-Nano side to the top pair on the VGA module side.
Solder the bottom wire from the DE0-Nano side to the bottom pair on the VGA module side.
See Picture 4 for more detail.

All done, now if you plug the VGA/PS2 module into the non-striped side of the connector, you'll be able to build designs including VGA and PS2.
Picture 5 is the whole lot connected up.

Pictures 6 and 7 show the test output on an LCD monitor.

I've attached a zip file containing pin files with the VGA and PS2 included, and the bit-stream file that you can load into the FPGA to display the test pattern on screen.

Enjoy your new VGA / PS2 capabilities.

Edit: Added pictures of test pattern display.

[Crazy Ape]

Added some pictures of the VGA output. Much more interesting than pictures of ribbon cable.

[Crazy Ape]

I thought a rotozoomed fractal background might make for an interesting display, even if not so useful. I've made a start, I still have to separate the 'Roto' from the 'Zoom', and add PS/2 keyboard support etc.

Some Details:
800 x 600 @ 72Hz refrash.
602 logic elements.
No vendor specific modules.
No RAM.
No framebuffer.
It should run on a large CPLD or any FPGA.

Both my camera and Youtube didn't like the moving image so the pics/vid don't look as good as live.

[ivan747]

Excellent contribution, I hadn't seen one like this in a long while! I've been wondering about getting an FPGA rev board, this is yet another reason. Thumbs up 

[Crazy Ape]

Excellent contribution, I hadn't seen one like this in a long while! I've been wondering about getting an FPGA rev board, this is yet another reason. Thumbs up 

Thanks for the comment, it was starting to seem pretty quiet in here.

Entry level dev boards are so cheap now days that it's well worth getting one if you think it may interest you.
This board at US $22.59 (delivered) would give you plenty to play with, without putting a hole in your bank account. If you decide FPGA's are of interest to you, you can look at a larger capacity device in future. This one won't let you build an Amiga etc, but will let you play around with design. The fractal rotozoomer would take up about 20% of that device.
http://www.aliexpress.com/item/ALTERA-FPGA-Cyslonell-EP2C5T144-Minimum-System-Learning-Board-Development-Board/1319801268.html

I'll post the full code (hmmm, for better or for worse) to the rotozoomer design here as an example once it's done.

[Crazy Ape]

I'll revisit the roto-zoom effect at a later time as I wanted to keep this small so people with large(ish) CPLDs don't miss out on the fun. Adding large lookup tables and the PS/2 controller put it out of reach for those people.

I'll find something else for the PS/2 (first post) port example.

I've tweaked the zoomer a little so it doesn't run off into the distance and will leave this design as just a demo effect.



Full VHDL source - Flame Away 

Code: [Select]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity RotoFractal is
    port(CLOCK_50 : in std_logic;
         VGAout:      out unsigned(10 downto 0); -- r2,r1,r0, g2,g1,g0, b2,b1,b0, hsync, vsync
         PS2_Clock:   in std_logic;
         PS2_Data:    in std_logic
         );
end RotoFractal;

architecture Behavioral of RotoFractal is

constant Black : unsigned(8 downto 0):="000000000";
constant White : unsigned(8 downto 0):="111111111";
constant Yellow : unsigned(8 downto 0):="111111000";
signal hcount : unsigned(10 downto 0):="00000000000";
signal vcount : unsigned(9 downto 0):="0000000000";
signal fraccount : unsigned(9 downto 0):="0000000000";
signal VGA, Out_Colour, ninecount : unsigned(8 downto 0):="000000000";
signal videoon, videov, videoh, hsync, vsync : std_ulogic:='0';
signal reset : std_ulogic:='0';
signal fraccountdir : std_ulogic:='1';
signal Yellow_Pixel, White_Pixel, Black_Pixel : std_ulogic:='0';
signal X0, X1, Y0, Y1 : unsigned(15 downto 0):="0000000000000000"; -- 65536 x 65536 virtual roto-plane
signal aa, bb : unsigned(7 downto 0);
signal aIN, bIN : unsigned(3 downto 0):="0000";
signal pOUT : unsigned(7 downto 0):="00000000";
function v4(a:unsigned;b:unsigned) return unsigned;
function v8(aa:unsigned;bb:unsigned) return unsigned;

function v4(a:unsigned;b:unsigned) return unsigned is
variable r0,r7 : std_ulogic:='0';
variable r2,r3,r4,r5,r6,t2 : unsigned(2 downto 0):="000";
variable r1,t3,t4,t5 : unsigned(1 downto 0):="00";
variable mid : unsigned(15 downto 0):="0000000000000000";

begin
mid(0)  := a(0) and b(0);
mid(1)  := a(1) and b(0);
mid(2)  := a(0) and b(1);
mid(3)  := a(2) and b(0);
mid(4)  := a(1) and b(1);
mid(5)  := a(0) and b(2);
mid(6)  := a(3) and b(0);
mid(7)  := a(2) and b(1);
mid(8)  := a(1) and b(2);
mid(9)  := a(0) and b(3);
mid(10) := a(3) and b(1);
mid(11) := a(2) and b(2);
mid(12) := a(1) and b(3);
mid(13) := a(3) and b(2);
mid(14) := a(2) and b(3);
mid(15) := a(3) and b(3);
r0:=mid(0);
r1(0):=mid(1) xor mid(2);     
r1(1):=mid(1) and mid(2);
r2(0):=mid(3) xor mid(4) xor mid(5) xor r1(1);
r2(1):=(mid(3) and mid(4)) xor (mid(5) and r1(1)) xor (mid(3) and mid(5)) xor (mid(4) and r1(1)) xor (mid(3) and r1(1)) xor (mid(4) and mid(5));
r2(2):=mid(3) and mid(4) and mid(5) and r1(1);
t2(0):=mid(6) xor mid(7) xor mid(8) xor mid(9);
t2(1):=(mid(6) and mid(7)) xor (mid(8) and mid(9)) xor (mid(6) and mid(8)) xor (mid(7) and mid(9)) xor (mid(6) and mid(9)) xor (mid(7) and mid(8));
t2(2):=mid(6) and mid(7) and mid(8) and mid(9);
r3 := t2 + to_integer(r2(2 downto 1));
t3(0):=mid(10) xor mid(11) xor mid(12);
t3(1):=(mid(10) and mid(11)) or (mid(11) and mid(12)) or (mid(12) and mid(10));
r4 := '0'&t3 + to_integer(r3(2 downto 1));
t4(0):=mid(13) xor mid(14);     
t4(1):=mid(13) and mid(14);
r5 := '0'&t4 + to_integer(r4(2 downto 1));
t5(0) :=mid(15);
r6 := '0'&t5 + to_integer(r5(2 downto 1));
r7 := r6(1);
return r7&r6(0)&r5(0)&r4(0)&r3(0)&r2(0)&r1(0)&r0;
end v4;

function v8(aa:unsigned;bb:unsigned) return unsigned is
variable pt1,pt3 : unsigned(7 downto 0);
variable pt2 : unsigned(8 downto 0);
variable aal,aah,bbl,bbh : unsigned(3 downto 0);

begin
aal := aa(3 downto 0);
aah := aa(7 downto 4);
bbl := bb(3 downto 0);
bbh := bb(7 downto 4);
pt1 := v4(aal,bbl);
pt2 := '0'&v4(aal,bbh)+v4(aah,bbl)+pt1(7 downto 4);
pt3 := v4(aah,bbh)+ pt2(8 downto 4);
return pt3&pt2(3 downto 0)&pt1(3 downto 0);
end v8;

begin
hcounter: process (CLOCK_50, reset)
begin
   if reset='1' then
      hcount <= "0000000000";
elsif (rising_edge(CLOCK_50)) then
      hcount <= hcount + 1;
      if hcount=1039 then
         hcount <= "00000000000";
end if;
end if;
end process;

vcounter: process (CLOCK_50, reset)
begin
   if reset='1' then
      vcount <= "0000000001";
elsif (rising_edge(CLOCK_50)) then
      if hcount = 1039 then
         vcount <= vcount + 1;
         if vcount = 665 then
            vcount <= "0000000000";
ninecount<=ninecount+1;
if fraccountdir = '1' then
fraccount <= fraccount + 1;
if fraccount > 512 then
fraccountdir <= '0';
end if;
end if;
if fraccountdir = '0' then
fraccount <= fraccount - 1;
if fraccount <= 1 then
fraccountdir <= '1';
end if;
end if;
end if;
      end if;
   end if;
end process;

process (vcount)
begin
   videov <= '1';
   if vcount > 599 then
videov <= '0';
   end if;
end process;

process (hcount)
begin
   videoh <= '1';
   if hcount > 799 then
videoh <= '0';
   end if;
end process;

sync: process (CLOCK_50, reset)
begin
   if reset='1'  then
      hsync <= '0';
      vsync <= '0';
elsif (rising_edge(CLOCK_50)) then
      hsync <= '1';
      if (hcount <= 987 and hcount >= 855) then
         hsync <= '0';
      end if;
      vsync <= '1';
      if (vcount <= 645 and vcount >= 636) then
         vsync <= '0';
      end if;
   end if;
end process;

PixelColourSelector: process (CLOCK_50,reset)
begin
if reset='1'  then
Out_Colour <= Black;
elsif (rising_edge(CLOCK_50)) then
Out_Colour <= Black;
if Yellow_Pixel='1' then
Out_Colour <= Yellow;
end if;
if White_Pixel='1' then
Out_Colour <= White;
end if;
if Black_Pixel='1' then
Out_Colour <= Black;
end if;
end if;
end process;

DrawApp: process (CLOCK_50, reset)

variable tmp1 : unsigned(15 downto 0):="0000000000000000";
variable tmp2 : unsigned(15 downto 0):="0000000000000000";
variable tmp3 : unsigned(15 downto 0):="0000000000000000";
variable tmp4 : unsigned(15 downto 0):="0000000000000000";
variable Xe0 : unsigned(15 downto 0):="0000000000000000";
variable Ye0 : unsigned(15 downto 0):="0000000000000000";

begin
if (rising_edge(CLOCK_50)) then
Yellow_Pixel <= '0';
White_Pixel <='0';
Black_Pixel <='0';

-- Very simple RotoZoom, Boing Boing Boing
if vcount = 0 then
X0 <= "0000000000000000";
Y0 <= "0000000000000000";
X1 <= "0000000000000000";
Y1 <= "0000000000000000";
elsif hcount = 0 then
X0 <= X1 - 65280;
Y0 <= Y1 + 65280 - ninecount;
X1 <= X1 - 65280;
Y1 <= Y1 + 65280 + ninecount;
else
X0 <= X0 + 65280 + ninecount;
Y0 <= Y0 + 65280;
end if;

-- Draw Fractal Thing
Xe0 := X0/256;
Ye0 := Y0/256;
if Ye0 >= 0 and Ye0 <= 256 and Xe0 >= 0 and Xe0 <= 256 then
tmp1 := (v8(Xe0(7 downto 0),Xe0(7 downto 0)));
tmp2 := (v8(Ye0(7 downto 0),Ye0(7 downto 0)));
tmp3 := (v8(256-Xe0(7 downto 0),256-Xe0(7 downto 0)));
tmp4 := (v8(256-Ye0(7 downto 0),256-Ye0(7 downto 0)));
if ((tmp1+tmp2) and (tmp1+tmp4) and (tmp2+tmp3) and (tmp3+tmp4)) <= fraccount then
Yellow_Pixel <='1';
end if;
end if;

-- Draw border
White_Pixel <='0';
if vcount <= 8 or vcount >= 592 or
hcount <= 8 or hcount >= 792 then
White_Pixel <='1';
end if;
end if;
end process;

   videoon <= videoh and videov;
   VGA <= Out_Colour;
   VGAout(10 downto 2) <= VGA and videoon&videoon&videoon&videoon&videoon&videoon&videoon&videoon&videoon;
   VGAout(1 downto 0) <= hsync & vsync;

end Behavioral;


[AwArD_RzD]

Thanks for the code (VHDL FTW), i'm waiting for a OV7660, i will try to do some motion sensor or maybe some filter effect, just need another screen. Your code will be a great help when i start this project.

[Crazy Ape]

Thanks for the code (VHDL FTW), i'm waiting for a OV7660, i will try to do some motion sensor or maybe some filter effect, just need another screen. Your code will be a great help when i start this project.

You'll have to factor in sine, cosine, and PI to make it useful for controlled image manipulation. It's basically a demo effect at the moment, though I'm thinking of using it as a background to a menu selection system.

[Crazy Ape]

I had some more time to play with this, and thought of simple function generator idea, I've attached it to the VGA timers for visual representation but it should be ok for audio out, something I'll get to later.

The function generator will track whatever function you can plot to the box, so I'll add a few other waveforms (might through together an audio function gen just for fun.)   

Once again, this is small enough to run on a CPLD.

No vendor IP blocks
No RAM
No Frame Buffer
No Sine Table
No Cordic core

Total Logic Elements: 481 (and that's mostly display oriented)

Video: (I know the camera is crappy)


Full Source Attached.

[marshallh]

That ain't any sine wave
BRAM LUT and call it a day. No reason to forgo it

[Crazy Ape]

Yes, you are correct, it's not sine, just an oscillatory wave of some description (at this point). I'll change it when I add waveform selections.

That ain't any sine wave
BRAM LUT and call it a day. No reason to forgo it

But where's the fun in that. I was trying to keep it small and general enough so even newcomers who might only have a CPLD can still join the fun.

[Crazy Ape]

As was so rightly pointed out:

That ain't any sine wave

Hmmm, call it a brain fart shall we, this one does better.

Not all that fast (slowed down for the cam here anyway) but fast enough for rotation etc.
Could also be used to re-populate a ram based sine table with different parameters.



Source attached.

[ivan747]

Very nice, you created sine and cosine without a look-up table.  Now if you remove the graphics you need no RAM and probably very little logic blocks. I'm still new to FPGAs as I haven't done a lot of electronics in the last months to be honest.

[Crazy Ape]

Very nice, you created sine and cosine without a look-up table.  Now if you remove the graphics you need no RAM and probably very little logic blocks. I'm still new to FPGAs as I haven't done a lot of electronics in the last months to be honest.

I'd still consider myself "new to FPGAs", I played about with a couple CPLD's for a month or so, then had to put it down for a year or so doing other stuff, I had a DE0-Nano sitting on the shelf, never opened and collecting dust, but a few posts here (or perhaps the lack of FPGA posts here) prompted me to have another play.

The SinCos engine takes very little logic on its own (and will take even less after I optimize it properly), it's all the other little bits, mostly stuff for the visuals but also for the multipliers (for CPLD compatibility).

[DJ027X]

Would you happen to have the project file for displaying your test image?

[rholdorf]

I'm a complete newbie regarding FPGA. But I want to learn, so I got the boards, Altera Quartus software, Crazy Ape's files and the modified flat cable. However, I have no idea how to put it all together.

I would appreciate if someone could point me to a tutorial (or perhaps write the steps here) on how to get those .pin .qdf and .sof files compiled and written onto the de0-nano, please.

Thank you!