Ok, fine. It's after 2AM here and I can't sleep. It's because I looked at another design I was going to manufacture where I have the same DDR/IC, and I got super scared when I realised the DDR there is routed using another 4 signal layers, but those are all stacked together and there is no ground/power plane in between, just adjacent to the first and fourth signal layer. I saw another post of yours, nctnico, where you are saying impedance starts becoming a factor only when traces are multiple cms long and hundreds of MHz, you were suggesting to focus on trace lengths. Do you think I can get away with that impedance-control-free-4-stacked-signal-layers design since that the maximum trace length is around 1cm? (still DDR400).
The stackup of the board discussed in this topic is better: ground, signal, signal, ground (repeat). There isn't half a mm of separation between the two signal layers as I saw in some application notes from Micron, unfortunately, it's just ~100um. By plugging the numbers in a calculator I get 73 Ohm for a microstrip and 58 Ohm by using the asymmetric stripline model, basically ignoring the second signal layer stacked between the two ground/power planes, that I guess makes sense and should say the impedance in there is not that wrong?
If that's the case, for this board, I believe the only improvements possible are the ones you suggested.
(I feel like a baby with being unable to sleep for this, but the idea of spending all that time again debugging this DDR scares me, and you convinced me there is work to do in here, nctnico).
Btw, Thank you for your time, again.