EEVblog Electronics Community Forum
Electronics => Microcontrollers => Topic started by: Digital_Treasure on February 21, 2018, 09:45:52 am
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Hello,
I have been giving a specification to derive 10MHz,5MHz and 1MHz from a 20MHz system clock. I am also supposed to design posedge and negedge flags for all the three derived clocks.
I used a 4 bit counter which counted from 0-15 and the counter[0] gave me the 10MHz clock signal and the counter [1] gave me the 5MHz signal. I used another 5 bit counter which counted from 0-9. I made my 1MHz signal register toggle for 0-9 each count, which gave me the 1MHz clock signal.
Now I am struggling to design the posedge and negedge flags for all three of the clocks. I used a combination logic of posedge = a^!b; but I could get the flags for 10MHz and 5MHz but couldn't extract my 1MHz flags from this method.
I was suggested to use my two counters (4 bit and 5 bit) to easily design the flags for all three of them. Kindly suggest on this
Thank you in advance and kind regards
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If I've understood correctly, why can't you just use a 5-bit counter that counts to 20? Then you just use combinatorial logic to get all six flags (posedge and neg edge for each derived clock). Unless I have missed something (happens)
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Please tell us what you mean by posedge and negedge flags.
A short pulse? An output lasting how long? Etc...
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Depending on your implementation (CPLD, FPGA, discrete logic)
IN a CPLD ofrr FPA could try a 20 bit shift register, clocked on every cycle
One loaded with 11111111110000000000 - will give 1 MHz
One loaded with 11001100110011001100 - will give 5 MHz
One loaded with 10101010101010101010 - will give 10 MHz
For discrete logic, use two D flipflops to divide by 2 and 4, and something like a CD4017 clocked by the 10MHz to give 1MHz.
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Thank you for your suggestion, if I use a 5 bit counter which counts from 0-19 and then toggles then I will have a divide by 40 clock cycles signal (in other words my period will be 40); so instead I have used a 5 bit counter which counts from 0-9 and toggles for every 10 clock cycles which is giving me a 1MHz clock.
I have used the combinational logic for the flags for 10 and 5 Mhz, its just unable to use the same thing for the 1MHz
because my snippet for 1MHz counter goes like this:
output clk_1MHz;
reg [4:0] counter_1MHz;
reg clk_1MHz_reg;
always@(posedge clk or posedge rst)
begin
if(rst == 1'b1)
begin
counter_1MHz <= 5'd0;
clk_1MHz_reg <= 1'b0;
end
else
begin
// ########### Logic to derive 1MHz from second-5bit counter ################
if(counter_1MHz == 5'd9)
begin
counter_1MHz <= 5'd0;
clk_1MHz_reg <= ~clk_1MHz_reg;
end
else
begin
counter_1MHz <= counter_1MHz + 5'd1;
clk_1MHz_reg <= clk_1MHz_reg;
end
end
assign clk_1MHz = clk_1MHz_reg;
since my clk_1MHZ_reg is not assigned from any counter value of the 5bit counter, Like in 10 & 5 mhz cases count[0] was assigned for 10 & count[1] was assigned for 5
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hello, thank you for your message. Its a pulse of 1 clock cycle of the 20MHz system clock
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As a Verilog beginner myself, I have to ask wouldn't something as:
output wire posedge_1MHz;
output wire negedge_1MHz;
...
...
assign posedge_1MHz = (counter_1MHz == 5'b0) && clk_1MHz_reg;
assign negedge_1MHz = (counter_1MHz == 5'b0) && !clk_1MHz_reg;
be enough to combinatorially generate the flags?
Edit: Actually, if my understanding is correct, it's in general better to avoid doing it combinatorially so I would rather write (with the flags as regs, not wires):
// ########### Logic to derive 1MHz from second-5bit counter ################
if(counter_1MHz == 5'd9)
begin
counter_1MHz <= 5'd0;
clk_1MHz_reg <= ~clk_1MHz_reg;
if(clk_1MHz_reg)
negedge_1MHz <= 1b'1; // clk_1MHz_reg will change to 0, so negedge
else
posedge_1MHz <= 1b'1; // clk_1MHz_reg will change to 1, so posedge
end
else
begin
// Reset the flags
posedge_1MHz <= 1b'0;
negedge_1MHz <= 1b'0;
counter_1MHz <= counter_1MHz + 5'd1;
clk_1MHz_reg <= clk_1MHz_reg;
end
end
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...
counter_1MHz <= counter_1MHz + 5'd1;
clk_1MHz_reg <= clk_1MHz_reg; // <<<<<< THIS line not needed >>>>>>>>
end
...
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...
counter_1MHz <= counter_1MHz + 5'd1;
clk_1MHz_reg <= clk_1MHz_reg; // <<<<<< THIS line not needed >>>>>>>>
end
...
You are of course right, I kept it as it was in the original code, but noticed it was redundant.
Thanks for pointing that out, as the difference between <= and = can be, for a beginner, quite confusing.
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Thank you for your suggestion, if I use a 5 bit counter which counts from 0-19 and then toggles then I will have a divide by 40 clock cycles signal (in other words my period will be 40); so instead I have used a 5 bit counter which counts from 0-9 and toggles for every 10 clock cycles which is giving me a 1MHz clock.
ahh you're right - I had a brain fart. A 6-bit counter is needed, counting from 0 to 39 would do, the 1MHz negative edge would be at count = 20, its positive edge pulse would be at 0.
I see you've used just 5-bits creating a pulse at 2MHz that toggles a register (clk_1MHz_reg <= ~clk_1MHz_reg), which is effectively doing the same thing.
I'm unsure why you wish to avoid combinatorial logic, I would create pulses for positive edges and negative edges combinatorially, but of course use these to toggle registers driven by the main clock.
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ahh you're right - I had a brain fart. A 6-bit counter is needed, counting from 0 to 39 would do, the 1MHz negative edge would be at count = 20, its positive edge pulse would be at 0.
I always find it easier to think in terms of periods, not frequencies.
The 20MHz period is 50 ns. If you count 40 of them it'll be 2 us. That's not what you need for 1 MHz.
You need to count to 10 (0 to 9). Then you get a period of 50*10 = 500 ns. Then you toggle it at the end. Holding the signal up for one counter period and down for the next one will give you 500 ns + 500 ns = 1 us - exactly what you need for 1 MHz.
You can get Posedge and Negedge through combinatorial logic:
Posedge is (counter == 0) & signal
Negedge is (counter == 0) & !signal
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Yup I noticed that shortly after posting, double brainfart.
Sorry for the confusion
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Thank you all of you, I did implement the design similarly, The only thing I am having a trouble understanding is if for 1MHz i need a counter that counts from 0-9 and toggles then I can do it with 4 bit counter isnt it? Why would I need a 5 bit counter?
I had designed it using a 5 bit counter and I am trying to do the same with 4 bit and no difference
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Why would I need a 5 bit counter?
You certainly don't need 5 bits.
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Whilst I don't want to confuse you further - I am already guilty of posting stuff that was far from helpful - you're correct that you only need a 4-bit counter.
If you generate a pulse that toggles a register/flipflop, then in a way you are dividing that pulse frequency by 2, or rather, multiplying its period by 2, since each pulse is creating a transition, and a period requires two transitions. So a counter, counting from 0-9, with a pulse at counter == 0, would create a pulse at the clock frequency / 10. 20MHz / 10 = 2MHz. Using that pulse train to toggle a register would mean that register toggles at 1MHz - so that toggled register can be thought of as a 5-th bit of the counter, its just not included in the counter as it is toggled outside of it.
It's a minor, and somewhat pointless detail, since what has been posted here works just fine.
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Just use a PLL (don’t take the advice of your boss or co-worker.) and be done with it.
For example, here are some: (many vendors and variants to choose from)
https://www.idt.com/products/clocks-timing/clock-generation/clocks-general-purpose (https://www.idt.com/products/clocks-timing/clock-generation/clocks-general-purpose)
I could do it for you but unfortunately I am a engineering consultant and prefer to work for $$.
@grouchobyte
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Just use a PLL ...
I don't think OP's professor would accept this solution :)