Do I get this timing chart right ?

[Back2Volts]

I need help with this timing chart from the ST7735 datasheet.    It is the timing for the bi-dir SPI + data/command line configuration.     My concern is with the D/CX signal line.    I am correct understanding that the driver reads the D/CX during the first clock period for the byte, that is the first bit being sent, and it does not care for its level for the rest of the byte ? 

I will appreciate your comments

Tony

[Back2Volts]

Based on this entry I found I may be wrong:

https://users.ece.utexas.edu/~valvano/arm/ST7735.c

// The Data/Command pin must be valid when the eighth bit is
// sent.

[Bruce Abbott]

That code sends the data in parallel to a hardware serializer, so it has no choice but to set D/CX for the entire period (even if the ST7735 does not require it).

According to figure 9.3.3, D/CX must be valid during the last bit of each byte. 
 

[Back2Volts]

Bruce, thank you.    I should have kept reading looking for more details.    Right around the picture you posted there is some text indicating DCX is sampled on the edge of the eighth SCLK cycle.

Tony