Hi,
I was planning to make a DSP based design. It was needed to be low-power so I decided to use TMS320C5505.
While examining the c5505 EMIF documents I come across with the following explanation: (you can reach from here pg87: goo.gl/n1fToS)
This device has limitations to the clock frequency on the EM_SDCLK pin (driven by SDCLK) based on the
CVDD and DVDDEMIF.
• When CVDD = 1.3 V, and DVDDEMIF = 3.3 V, 2.75 V, or 2.5 V, the maximum clock frequency on the
EM_SDCLK pin is limited to 100 MHz (EM_SDCLK ? 100 MHz). Therefore, if SYSCLK ? 100 MHz, the
EM_SDCLK can be configured either as SYSCLK or SYSCLK/2, but if SYSCLK > 100 MHz, the
EM_SDCLK must be configured as SYSCLK/2
So basically -as far as I understand- it says you need to choose an SDRAM that works half of the clock rate of your DSP. I went an searched the SDRAMs in digikey. But all of the devices were working above 100MHz. So they are not suitable for using with that chip. (Unless I somehow could use in lower clockrates.) So I deduced that SDRAM are meant to be used with "not so much low-power" devices running at least couple hundreds of MHz?
But then I look the memory map of this chip, c5505, and half of its adress space is for SDRAM. So I am quite in doubt about my deduction. Does my assumptions are correct? How can I supply the need for extra RAM using this chip?