Hello!

I am currently working on a university project for which I have a state machine with some state transition logic.

One of the requirements of this project is to do a manual schematic entry of the FSM state transition logic.

In order to make my life a tad bit easier, I wrote a Verilog test bench that applied all possible inputs to the behavioral description of the state transition logic and then recorded the corresponding outputs.

I used that data to define a logic function in

Logic Friday via the CSV import.

Unfortunately my state vector is 6 bits long as I have 54 states to represent. Including flags from the ALU and a reset and load signal my total number of inputs is 10 bits and I am outputting 6 bits.

This means I have 1024 possible input combinations.

Discarding half of the times where the reset signal is high that still leaves 512 combinations that have to be checked.

The way I'm currently verifying the schematic entry version is to simply use the schematic view of my FSM logic in the previously mentioned test bench and

looking at the input and output bit patterns for the behavioral and schematic version by viewing the differences between the two resulting text files in a text editor.

You can view both files and their differences on GitHub:

https://github.com/g4lvanix/sse-eevblog/commit/bb008412cc44cc3f9f2b6238bbb35deea1285844?diff=splitIn my case I have a couple of repeating combinations where one of the bits is incorrect.

Is there a systematic way to figure out where in the schematic things are going awry?

The schematic is rather large with 114 gates and I have no idea how to properly debug such issues systematically.

I have attached the schematic just so you know what I'm looking at and why I need an efficient way of debugging this issue.

Any help is greatly appreciated!

galvanix