Hi everyone, first time post here.
I've been playing around with FPGAs on-and-off for a while now, but I'm still quite new to them and I have a question about the best practices to use when you're writing VHDL processes. I realize that what I'm asking here is probably very vague, but everything I've learned about FPGAs so far has been self-taught (insofar as anything you learn on the internet is "self-taught") and I could really use some guidance from people who know how these things should be done. My question concerns how you should split logic in a single entity across processes.
The most basic example I can come up with is simulating and synthesizing the TTL 7400 quad-nand chip. There are 3 ways I can think to do this. First is the most obvious and the most easiest to read, at least to me, when you're sticking with discrete std_logic signals:
process(A1, A2, A3, A4, B1, B2, B3, B4)
begin
Y1 <= A1 nand B1;
Y2 <= A2 nand B2;
Y3 <= A3 nand B3;
Y4 <= A4 nand B4;
end process;
Second is to minimize the work done in each process, as well as the dependency lists:
process(A1, B1)
begin
Y1 <= A1 nand B1;
end process;
process(A2, B2)
begin
Y2 <= A2 nand B2;
end process;
// ...etc...
Third is to exploit parallelism and use vectors:
-- A, B and Y are now all std_logic_vector(3 downto 0)
process(A, B)
begin
Y <= A nand B;
end process;
My intuition is telling me that #3 would typically be more helpful to the synthesizer and thus the most most preferred of the three. I'm also guessing that #1 would be second choice because while it would (in theory) slow down simulation it's much easier to read. If simulation started becoming an issue then I'd start looking at #2...although as a beginner I have no idea whether that even happens.
Can anyone give me some general guidelines as to the circumstances in which you would use these or if there are any others that I'm missing?