fpga boards: curious about projects that *you* do, guys

[rstofer]

Also, computers a 1000 times faster than the systems I grew up with, so why is it that they are slower to start-up and I'm still waiting on the computer to do things??

Depends on how the machine is put together. I recently built a new machine with an AMD Ryzen CPU and an M.2 NVME SSD as the system disk. This system gets to the Windows 10 login screen six seconds after pressing the power button. Once booted, the machine is very fast and responsive with no perceptible lag when doing any typical task.

On my new machine, it isn't Win10 boot that takes time, it's the BIOS.  Actual boot of Win 10 is just a couple of seconds from the splash screen to the login screen.

The I7 7700K and a very fast M.2 SSD make all the difference.  I looked at one of the high end Ryzen CPUs and they looked really good.  Unfortunately, Vivado won't use more than 8 threads and, more often than not, it won't use more than 2.  Having a multi-chip bazillion thread Xeon machine (floor heater) won't help.  At least for the WebPack version.

In any event, my simple LC3 project times something like:  55 seconds to synthesize, 55 seconds to implement and 10 seconds to write the bit file.  Two minutes is an enormous improvement - even if the project is only about 1000 lines of code.  In the bad old days of slower machines, I had a project that took 20 minutes to run ISE.  I can't imagine what it would have taken for Vivado.

Speed is good!  How fast can you afford to go?

[dnotq]

Pong Chu has also written "RTL Hardware Design Using VHDL...", again, pretty expensive.  I have this book and it's excellent.

I also have that book, and yes it is excellent just like his FPGA Prototyping By VHDL Examples book.  However, IMO the RTL Hardware Design book should be read once you have a good handle on working with FPGAs, since it is very heavy in HDL analysis rather than making things.

I think I am more interested in books that present a project.

That's why I suggested Pong's FPGA Prototyping By VHDL Examples book.  He even wrote a version for Verilog if that is your thing.  It is expensive, but worth it IMO, and it is very project oriented.  Pong gives you enough information about a topic, then takes you through projects that demonstrate the topic being learned.  It starts off with some projects like PWM LED control, shifting techniques, from FSM introductions, etc.  Then he moves into chapters that show how to make a working UART, PS2 Keyboard an mouse interface, external SRAM controller, VGA controller, then ties it all together by implementing a PONG game.  At the end of the book he shows how to work with a Xilinx PicoBlaze core.

[Sal Ammoniac]

On my new machine, it isn't Win10 boot that takes time, it's the BIOS.  Actual boot of Win 10 is just a couple of seconds from the splash screen to the login screen.

There are usually BIOS settings to make the startup complete quicker. Often it's just sitting there for a few seconds waiting for you to hit DEL or F2 to get into BIOS setup.

Unfortunately, Vivado won't use more than 8 threads and, more often than not, it won't use more than 2.  Having a multi-chip bazillion thread Xeon machine (floor heater) won't help.  At least for the WebPack version.

Eventually companies like Xilinx will realize they're in the business of selling chips, not software, and this nonsense will go away.

[legacy]

Eventually companies like Xilinx will realize they're in the business of selling chips, not software, and this nonsense will go away.

Eventually, next time he will come down town, Santa Claus will probably give you a basket of coal!

Even Santa knows that that Software like Cadence Allegro costs more money than a flat just in license, while ISE and Vivado having being been released as Xmas gift, you can download them, and use them in a features-reduced version without paying a penny.

Thus, it's like you're pissing on Santa's shoes as your personal complaining that you want more feature in the gift that he is giving you.

Does it make sense? Sure, cold winter, have a basket of coal 

[legacy]

Ups. this is the book I was talking about.

[rstofer]

That's why I suggested Pong's FPGA Prototyping By VHDL Examples book.  He even wrote a version for Verilog if that is your thing.  It is expensive, but worth it IMO, and it is very project oriented.  Pong gives you enough information about a topic, then takes you through projects that demonstrate the topic being learned.  It starts off with some projects like PWM LED control, shifting techniques, from FSM introductions, etc.  Then he moves into chapters that show how to make a working UART, PS2 Keyboard an mouse interface, external SRAM controller, VGA controller, then ties it all together by implementing a PONG game.  At the end of the book he shows how to work with a Xilinx PicoBlaze core.

In the spectrum of things FPGA, I don't know where I sit.  While I can code up anything I am likely to need, I am certain there are 'better' ways to do it.  'Better' is subjective but that's the kind of thing I am looking for.  I want to see how others have done a complete project.  How they started with an ISA and broke it up into one of more FSMs.  Where they used integers, where they used SLVs, why in the world they used variables for anything other than loop counters, that kind of thing.

There's a lot of bitching on the Internet about projects that are 100% SLVs but when you pick up a bit of code off the Internet, sure enough, it is all SLVs.  And I'm not about to start a religious war over unsigned versus SLV but I would like to see what gets synthesized.  I don't care a bit about how it gets simulated, simulation isn't hardware and the only thing I care about is hardware.

I spent some time with the RTL Schematic view in ISE.  I haven't tumbled to that feature in Vivado.  But ISE is good enough to see how the circuits differ.  And, if they don't differ, then the whole discussion is Ford versus Chevy.  Because what gets implemented is SLVs.  Hardware better not be anything else.

I guess it is this corner of the HDL sandbox that interests me.  The stuff at the margins.  I already know how to create all the building blocks in several different ways and I have several very good books to help.  But it is always interesting to see how someone else does things from beginning to end.

[rstofer]

Ups. this is the book I was talking about.

I ordered a used copy from Amazon, it'll be here Monday.  I have next to no interest in ASICs or silicon, I'm long retired!  Nothing I build will be of any interest to anybody.

I have been wanting to learn more about Verilog.  I just don't 'get it' so maybe this will broaden my horizons.  It's kind of like wanting to learn COBOL after programming business applications in FORTRAN.  You get the same answers but the code looks a lot different!  And just when you think you have a handle on things, along comes PL/I.

It still gets down to patterns.  A MUX is coded this way, an FSM like this.  Learn the patterns and just link blocks together.

[rstofer]

On my new machine, it isn't Win10 boot that takes time, it's the BIOS.  Actual boot of Win 10 is just a couple of seconds from the splash screen to the login screen.

There are usually BIOS settings to make the startup complete quicker. Often it's just sitting there for a few seconds waiting for you to hit DEL or F2 to get into BIOS setup.

That is true, I can set the BIOS for fast boot.  Since I only boot once a day and it takes perhaps 15 seconds, I just don't care enough to wade through the BIOS menus looking for the option.  And, yes, it is in the User Manual.  Just not something I care about.

Unfortunately, Vivado won't use more than 8 threads and, more often than not, it won't use more than 2.  Having a multi-chip bazillion thread Xeon machine (floor heater) won't help.  At least for the WebPack version.

Eventually companies like Xilinx will realize they're in the business of selling chips, not software, and this nonsense will go away.

I'm not sure that the 'for pay' version uses any more threads than the WebPack.  When I researched the answer, the limitation didn't say anything about WebPack versus 'for pay'.

It's taken me a while but I'm finally getting to enjoy Vivado.  Not that I'll ever get away from ISE, I have too many Spartan 3 boards.

[legacy]

limitation didn't say anything about WebPack versus 'for pay'.

I remember something about ISE v10.1-v14.7, anyway I can confirm you that there is an huge difference between the WEBPack and the FULL license version.

We have a couple of copies at work, they don't have any limitation on usable threads, and the same software on the hardware with the same project gives you results in different times and it depends on having the license enabled/disabled.

Last time I wanted to check:

License Valid & License Enabled -> extremely fast on large projects, no matter how much complex the project goes

No license | no Valid License | License Disabled -> time results depend on the project's complexity
a) -> largely slow on large projects!
b) -> lightly slow on simple small projects (<1000 lines)!

Sonata Simili and Sigasi have the same behavior: the free license is limited and slower by several orders of magnitude when the project is large and doesn't use threads.

We don't use Vivado 

By the way, consider yourself "lucky" of having the free WebPack, some UNIX solutions don't come with any free version and you have to pay for the license, otherwise the program doesn't run at all.  Oh, and the licence is something like 20-50K euro per year!

edit: p.s.
on old Altera tools there was a trick: if you agreed with "I want to give statistic(1) back to Altera" they give you a bonus acceleration. It is an hidden button to be clicked and a some lines to read and  to agree. I don't remember precisely where what etc.

(1) I just remember that it was like: which chip you mainly use? how many lines of code? VHDL or VERILOG? which is the used simulator? External? Internal? how many magic functions got used? how many IP? which IP? etc ...

[legacy]

back to the topic, I am still trying to improve the division algorithm
(and it is still too slow  )

[rstofer]

By the way, consider yourself "lucky" of having the free WebPack, some UNIX solutions don't come with any free version and you have to pay for the license, otherwise the program doesn't run at all.  Oh, and the licence is something like 20-50K euro per year!

If it wasn't for free tools, I couldn't play with FPGAs at all.  I never look a gift horse in the mouth.  I'm totally pleased with both ISE and Vivado.  I haven't used it much but the free Altera Quartus tool seems to work pretty well and I have installed the Lattice tools but haven't got around to using them.

Free is good!  Even if Xilinx does collect usage information from WebPack users.

I think there will always be a requirement for a 'student' edition and it will probably be free or very close to free.  The manufacturers need to get students locked into their devices as early as possible.

[legacy]

Free is good!

It's obnoxiously irritating when Xilinx/Altera/whoever releases something for free with some feature limited (e.g. threads) and people complain that they want *ALL* for free!

This is always the point! You give them a thumb, they want the the whole arm

Some time ago I read about people who wanted ISE's source code in order to recompile it on their Linux/ARM (tablet? SBC? does it make sense?) so they can -1- remove limitations and -2- run the binary on modern OSs

Thought: are they kidding?

No, they were serious! They actually believed that it was a reasonable question, probably because they believe that "since Xilinx sells chip, then the software MUST be OpenSource"
 
OMG too much OpenSource has given them a mind-bug 

[NorthGuy]

I don't think the "paid for" Vivado is any faster than WebPack. If it was, Xilinx wouldn't keep this in secret.

If you're using small Artix-es, Vivado may look expensive.

If you're forking over $20K for fast Virtex, paying for Vivado is peanuts.

[rstofer]

I don't think the "paid for" Vivado is any faster than WebPack. If it was, Xilinx wouldn't keep this in secret.

If you're using small Artix-es, Vivado may look expensive.

If you're forking over $20K for fast Virtex, paying for Vivado is peanuts.

I guess it depends on who is paying for it.  Us pensioners have to watch how we spend money!
I don't care if the WebPack is slowed, I've got nothing but time.  No deadlines, no commitments, just mental exercise.

[brucehoult]

No, they were serious! They actually believed that it was a reasonable question, probably because they believe that "since Xilinx sells chip, then the software MUST be OpenSource"

OpenSource is a bit far, since it would help other FPGA manufacturers.

I can't see what use Vivado is is you don't use Xilinx FPGAs though. I guess you could just use it for simulation. But they would not sell one FPGA fewer if unrestricted Vivado was free, and they might sell a lot more.

Apple was charging for MacOS updates for a while, but eventually they understood it's far less hassle for support if everyone is on the same version, and the Mac and iPhone hardware sales is where the money is.

[hamster_nz]

I can't see what use Vivado is is you don't use Xilinx FPGAs though. I guess you could just use it for simulation. But they would not sell one FPGA fewer if unrestricted Vivado was free, and they might sell a lot more.

I think it might be caused by accounting practice. If a company spends a lot of time investing money into building something (e.g. Vivado), then the have a big asset on the books, and have a business unit to support and develop it. And if they have this asset they have to work out how it make return on that investment. After all, if they didn't develop the tools themselves, they would need to license the tools from somebody else for $$$

So saying that this big multi-million $ asset has has no commercial value and giving it away for free sounds wrong, I assume in America the directors could be sued by shareholders for not maximizing profit. It also sounds wrong to load up the prices of the chips to allow the chip-making part of the business pay for it - the tools are not really involved in manufacturing the silicon (they would use very expensive licensed ASIC tools for their design work).

Giving the tools away for free most likely looks like "not in the shareholders best interest" when you have what looks to be a somewhat profitable development & support business units.

[brucehoult]

I can't see what use Vivado is is you don't use Xilinx FPGAs though. I guess you could just use it for simulation. But they would not sell one FPGA fewer if unrestricted Vivado was free, and they might sell a lot more.

I think it might be caused by accounting practice. If a company spends a lot of time investing money into building something (e.g. Vivado), then the have a big asset on the books, and have a business unit to support and develop it. And if they have this asset they have to work out how it make return on that investment. After all, if they didn't develop the tools themselves, they would need to license the tools from somebody else for $$$

So saying that this big multi-million $ asset has has no commercial value and giving it away for free sounds wrong, I assume in America the directors could be sued by shareholders for not maximizing profit. It also sounds wrong to load up the prices of the chips to allow the chip-making part of the business pay for it - the tools are not really involved in manufacturing the silicon (they would use very expensive licensed ASIC tools for their design work).

Giving the tools away for free most likely looks like "not in the shareholders best interest" when you have what looks to be a somewhat profitable development & support business units.

Sometimes accountants try to make businesses do all kinds of perverse things. It's the executives job to resist that.

If Vivado was an unrelated product to FGPAs then  it would be correct to run it as a different profit center, and try to recoup the costs of developing it from software sales.

But it's not. If they didn't have Vivado (whether developed in-house or bought in) they would sell a big fat *zero* FPGAs. Having the software is a cost of being in the FPGA business. It simply can't be accounted separately.

[NorthGuy]

I think it might be caused by accounting practice. If a company spends a lot of time investing money into building something (e.g. Vivado), then the have a big asset on the books, and have a business unit to support and develop it. And if they have this asset they have to work out how it make return on that investment.

Pure non-sense. They also spent lots of money developing assets for advertising campaigns. Would you say they now need to work on the way to sell their ads instead of showing them for free?

They wouldn't sell any of the chips, IPs etc. if they didn't have tools. Similarly, they wouldn't sell anything if they didn't have buildings, tables, printers and other stuff. These all are assets which do not bring any direct revenue (and quietly depreciate over time). The goal of these assets is to support sales of the chips. The revenue they get from selling Vivado is insignificant. "High" price is simply a method to pump-up the perceived value of their software.

If Vivado was owned by a separate company where it was the sole revenue source, the price, representation, everything would be different. For example, Xilinx would have to pay a lot for using the Vivado software as a venue for selling IPs, which would be a nice revenue source for Vivado company.

[Cerebus]

... "High" price is simply a method to pump-up the perceived value of their software.

It's not even that, it's almost pure classical "rent-seeking".

[joeqsmith]

talking about suggested fpga boards has made me a bit curious about projects (which kind) that you do guys

here I am focused on softcore & its debug processor (my own design, looooong story, looooooooong time project), and STN LCD drivers.

what about you?

The last larger home project was my HIL simulator for one of my bikes.  Basically everything is done in the FPGA from simulating the sensors to reading the fuel and timing information. 

[legacy]

HIL simulator for one of my bikes.  Basically everything is done in the FPGA from simulating the sensors to reading the fuel and timing information.

HIL stands for hardware in the loop. Right?
Does the timing information come from the combustion engine?

Interesting project 

[joeqsmith]

HIL simulator for one of my bikes.  Basically everything is done in the FPGA from simulating the sensors to reading the fuel and timing information.

HIL stands for hardware in the loop. Right?
Does the timing information come from the combustion engine?

Interesting project 

Sorry, yes Hardware In the Loop.   There is a engine, vehicle model running on the PC.   The actual ECM  (Engine Control Module) plugs into the simulator.  The idea then is the ECM thinks it is running on the real vehicle.   The ECM controls the fuel and ignition timing.   The FPGA decodes this information and passes to the engine model.  Likewise, the models then passes information back to the FPGA. 

Sorry but due to some background music, YT flagged most of my videos of it.   This is a fairly old video but gives some idea how it works.  The simulator today has no C code at all.  Everything is done in LabVIEW including the interrupt (event) handler.  I bought a new PC and it was just so fast, it needed something to do.... 






 

[legacy]

WOW impressed 

[joeqsmith]

WOW impressed 

There is a technical side playing behind a keyboard which I enjoy but nothing beats putting things into practice. 

[legacy]

There is a technical side playing behind a keyboard which I enjoy but nothing beats putting things into practice. 

You! You do a lot of interesting stuff, man