FPGA configuration memory: Selecting appropriate size

[tszaboo]

55 nm CPLD ( lil'FPGA )? I can only hope they can fit the bigger devices into that QFP package, not one of these joke size 32 MC ones.

There is nothing CPLD about it. Like I said before it is the Cyclone arch with some other stuff integrated onto a smaller die and with smaller/denser package options. It is for all intents and purposes a FPGA

MAX10 will be FPGA. It will support DDR2/DDR3 memories (Cyclone IV doesn't) and will be capable of running Nios.

Be aware guys of Platform L. But now - 

OK, it was confusing that they listed under CPLDs and used a CPLD name for it. I'm not that familiar with Altera.

[Dago]

MAX 10 sounds interesting. I bet they will screw it up with huge packages though. I'd love to have a "small FPGA" with something like a QFN48 package. I think Lattice had something but after seeing the train wreck software from Xilinx (compared to Quartus) I'm not too keen on trying out other chips than Altera

[mikeselectricstuff]

MAX 10 sounds interesting. I bet they will screw it up with huge packages though. I'd love to have a "small FPGA" with something like a QFN48 package. I think Lattice had something but after seeing the train wreck software from Xilinx (compared to Quartus) I'm not too keen on trying out other chips than Altera

Ditto - QFP/QFN 48 and 64 packages are a gaping hole in the FPGA market. I want devices that can be used on a 2 layer PCB, so QFN/QFP not BGA, and onboard core voltage reg help a lot, though. Seperate Vcore can be doable if the pin locations are sensible. 
The reason I like XO2 so much is you need no additional parts, not even an oscillator - 3.3v in and off you go.

Lattice do a  QFN32, but it wastes a of pins on 4 bank supplies (21 IOs available) and has no PLL or blockram.
They do however have a way to re-use JTAG pins as I/Os, just needing a single dedicated JTAG enable pin to switch between JTAG and IO.
But the next step up from that is QFP100.

Lattice software seems fine - I've not done anything too complex but compile times are OK- about 20 secs for a simple design, and you can select which devices to install. Avoid the integrated Diamond programmer though - way slower than the standalone version.