FPGA configuration memory: Selecting appropriate size

[gregallenwarner]

I've been studying FPGA design and VHDL programming for several months now. I've successfully designed, built, and used little CPLD based devices, and now I'm needing to use an FPGA for greater logic capacity. I'm looking at FPGA configuration memory IC's on Mouser right now (Altera brand), and I'm seeing various sizes ranging from 1M to 32M. How do you know how much configuration memory your compiled VHDL program will require? Does the Quartus II software display this anywhere after compiling the design so I know which IC to buy? (Sorry if I'm overlooking something obvious. I'm still learning the feature set of Quartus.)

Thanks for your help.

[Bassman59]

I've been studying FPGA design and VHDL programming for several months now. I've successfully designed, built, and used little CPLD based devices, and now I'm needing to use an FPGA for greater logic capacity. I'm looking at FPGA configuration memory IC's on Mouser right now (Altera brand), and I'm seeing various sizes ranging from 1M to 32M. How do you know how much configuration memory your compiled VHDL program will require? Does the Quartus II software display this anywhere after compiling the design so I know which IC to buy? (Sorry if I'm overlooking something obvious. I'm still learning the feature set of Quartus.)

The size of the configuration image is fixed for a given FPGA device, and this is regardless of the design complexity. It doesn't matter whether the design (not the "program") is nothing more than a simple AND gate or a data-processing engine that uses 90% of the resources: all of the configuration cells in the device need a valid setting.

And the device's family data sheet will always tell you the exact size of the configuration image, so you simply need to choose a configuration EEPROM that's large enough to hold that image.

[gregallenwarner]

Ah, thanks. I had tried looking in the datasheet first, but as it turns out, Mouser's datasheet link just linked to the "Product Overview" sheet from Altera, which didn't specify the required configuration device. I needed to go on Altera's website for the configuration memory device lists. Thanks again.

[Stebanoid]

If it helps, data you need contains in "configuration guide" at Xilinx. May be Altera have similar name for that document.

[mikeselectricstuff]

Size will be in the datasheet, in the section that talks about configuration.
There is no need to use expensive dedicated config memories these days as most FPGAs can use cheap SPI flash memory.

[gregallenwarner]

Size will be in the datasheet, in the section that talks about configuration.
There is no need to use expensive dedicated config memories these days as most FPGAs can use cheap SPI flash memory.

This is of particular interest to me, as Altera's config memories are expensive! (>$10 a pop!)
I'm going to Google how to do this. Thanks!

[mrflibble]

I'm going to Google how to do this. Thanks!

This info is in the altera/xilinx documentation. Should be called something like "configuration user guide", at least that's the doc name for xilinx.

Edit: doh, I see this was already mentioned. Ah well, since you apparently didn't find the info yet I guess it doesn't hurt to mention it doubleplusplus.

[marshallh]

Get the altera cyclone handbook. The "datasheet" is just the electrical specs, there's many more pages out there.

Odds are if you're asking the question an EPCS4 will work for you, but check against the specific device you're using

[mikeselectricstuff]

Size will be in the datasheet, in the section that talks about configuration.
There is no need to use expensive dedicated config memories these days as most FPGAs can use cheap SPI flash memory.

This is of particular interest to me, as Altera's config memories are expensive! (>$10 a pop!)
I'm going to Google how to do this. Thanks!

I gather that Altera were very late into the game of officially supporting SPI flash, but it has been possible for a while, just not well documented.
I think Xilinx were first to support SPI flash , with the S3, where the FPGA cost less than their config memories!

[gregallenwarner]

I gather that Altera were very late into the game of officially supporting SPI flash, but it has been possible for a while, just not well documented.
I think Xilinx were first to support SPI flash , with the S3, where the FPGA cost less than their config memories!

So, in your opinion, do you think it'd be easier to go with Xilinx then, if my intent is to use cheap SPI flash memory? I'm only considering Altera at present because I already have a USB Blaster clone, and I've done some work with the MAX3000A line CPLD's so far, so I'm familiar with Quartus. But if you think it'll save me some future headache going with Xilinx, the cost savings would be worth it to me if I could use SPI flash. Lowering the cost of the BOM is my primary design strategy.

I did find all those other documents being mention above, by the way. Thank you all for pointing me in the right direction. This is my first time dealing with chips complicated enough to have more than one datasheet, and I'm not used to that concept! But I'm slowly getting the hang of it! 

[mikeselectricstuff]

I gather that Altera were very late into the game of officially supporting SPI flash, but it has been possible for a while, just not well documented.
I think Xilinx were first to support SPI flash , with the S3, where the FPGA cost less than their config memories!

So, in your opinion, do you think it'd be easier to go with Xilinx then, if my intent is to use cheap SPI flash memory? I'm only considering Altera at present because I already have a USB Blaster clone, and I've done some work with the MAX3000A line CPLD's so far, so I'm familiar with Quartus. But if you think it'll save me some future headache going with Xilinx, the cost savings would be worth it to me if I could use SPI flash. Lowering the cost of the BOM is my primary design strategy.

I did find all those other documents being mention above, by the way. Thank you all for pointing me in the right direction. This is my first time dealing with chips complicated enough to have more than one datasheet, and I'm not used to that concept! But I'm slowly getting the hang of it! 

I think this was quite a while ago - I'm told Altera do support SPI flash but haven't looked at how well documented it is - check the documentation for details.

[gregallenwarner]

Will do. Thanks!

[miguelvp]

This might help

http://www.newark.com/pdfs/techarticles/spansion/Configuring_Altera_FPGAs_via_SPI_Flash_AN_01_e.pdf

The problem is that Altera's documentation always refers to SPI as Active Serial (AS) I guess in an effort to sell their chips?

Edit: link to Altera's configuration web page with lots of details around links and sub sections.
http://www.altera.com/support/devices/configuration/cfg-index.html

[gregallenwarner]

Thanks again! Those are good resources. I'm adding them to my (ever growing) list of documentation!

You guys have been a big help here. Thanks!

[marshallh]

Active Serial == SPI

Altera's EPCS configuration devices are just.... rebranded ST NOR Flash

M25P40 is exactly the same silicon as EPCS4
You can also use M25P80 in its place. $1
M25P16 is exactly the same silicon as EPCS16

and so on.

Note that some of the older Cyclone series are only tested against that exact silicon, and may not work with say Winbond or MC flash.

Altera supports Signaltap ILA with their free Quartus.... Xilinx doesn't. Absolutely huge difference there, let alone the quality of rest of the design suite.

[mikeselectricstuff]

Active Serial == SPI

Altera's EPCS configuration devices are just.... rebranded ST NOR Flash

That would explain why there were reticent in documenting...!

M25P40 is exactly the same silicon as EPCS4
You can also use M25P80 in its place. $1

Spansion 8Mbit SPI flash is GBP0.20 1-off!
http://www.digikey.co.uk/product-detail/en/S25FL208K0RMFI041/1274-1051-ND/3862736

Altera supports Signaltap ILA with their free Quartus.... Xilinx doesn't. Absolutely huge difference there, let alone the quality of rest of the design suite.

I've heard that Altera software is good - not used it myself.
Altera have historically been a bit lacking in lowest-end devices compared to Xilinx and Lattice, but as it's a competitve market I expect pricing is similar for similar capabilities.
Unfortunately like all the others they haven't done anything to fill the gaping  sub-100 pin hole in the low-end market

[miguelvp]

I've heard that Altera software is good - not used it myself.
Altera have historically been a bit lacking in lowest-end devices compared to Xilinx and Lattice, but as it's a competitve market I expect pricing is similar for similar capabilities.
Unfortunately like all the others they haven't done anything to fill the gaping  sub-100 pin hole in the low-end market

Well, they are promoting their Max CPLDs to full fledged non-volatile FPGAs on their incoming Max 10. Even the Max V was more FPGA than CPLD but being non volatile.

http://www.altera.com/devices/fpga/max-10/max-10-index.htmlhttp://www.altera.com/devices/fpga/max-10/max-10-index.html

The Max 10 is big enough to run the Nios II soft core.

http://www.altera.com/devices/cpld/max-about/max-about.html

[marshallh]

The Max 10 is absolutely the next chip I'm most excited about. It's what they should've made the next Cyclone (instead they backported the stratix arch to the cyclone series and bumped the min price)
Unfortunately I can't tell you about all the cool aspects of the MAX10 due to NDA but the silicon is just getting out there and it is very well suited for the lowcost area. It's basically the good ol' Cyclone arch on 55nm
They even provide a QFP package option.

[mikeselectricstuff]

They even provide a QFP package option.

Almost everyone does, but unfortunately they tend to start at 100 pins

[deephaven]

The Max 10 is absolutely the next chip I'm most excited about. It's what they should've made the next Cyclone (instead they backported the stratix arch to the cyclone series and bumped the min price)
Unfortunately I can't tell you about all the cool aspects of the MAX10 due to NDA but the silicon is just getting out there and it is very well suited for the lowcost area. It's basically the good ol' Cyclone arch on 55nm
They even provide a QFP package option.

That sounds like a nice device. I'm currently using Cyclone 2 and 3 devices.

Trouble is, I would have to get the latest version of Quartus to use the new device. I'm currently on V9.1 as it is the last one to support easy simulation, I wish they hadn't taken that away! Call me old fashioned but I still also use mainly schematic entry rather than this VHDL or Verilog stuff 

[gregallenwarner]

Active Serial == SPI

Ok, so I've wrapped my mind around this much so far. But what about the chip commands? I may still be failing to understand something basic here, but as I've been reading endless amounts of datasheets, I see that these SPI Flash chips have certain command codes that need to be shifted into them in order to tell it whether you're doing a read, a write, giving it a target address, etc.

Are these command codes going to be compatible with the "language" spoken by Altera's FPGA's for their native AS configuration mode?

Again, if I'm way off base about something, let me know.

I did notice how MaxV looked more like an FPGA internally than a true CPLD, and considered ordering some to test out. Max10 sounds like a pretty exciting upgrade. 100 pin QFP's don't scare me! 

[mikeselectricstuff]

Active Serial == SPI

Ok, so I've wrapped my mind around this much so far. But what about the chip commands? I may still be failing to understand something basic here, but as I've been reading endless amounts of datasheets, I see that these SPI Flash chips have certain command codes that need to be shifted into them in order to tell it whether you're doing a read, a write, giving it a target address, etc.

Are these command codes going to be compatible with the "language" spoken by Altera's FPGA's for their native AS configuration mode?

Again, if I'm way off base about something, let me know.

I did notice how MaxV looked more like an FPGA internally than a true CPLD, and considered ordering some to test out. Max10 sounds like a pretty exciting upgrade. 100 pin QFP's don't scare me! 

SPI flash commands are generally the same for all makes, certainly for reads which is all the FPGA needs to know.
ISTR on the first Xilinx parts that supported SPI there were a few options on the config pins to select different SPI flash types but I think they are now sufficiently standard that this isn't necessary.
The area where you may see issues is in programming. I don't know about Altera, but with Lattice, their ispVM SW loads up a small temporary RAM config which maps the SPI pins to the JTAG pins, so the software can talk to the SPI flash direct. It checks the device signature to determine the programming algorithm, and only supports the chips it knows about (which is quite a wide range). 
So in principle any FPGA that supports SPI flash will support any SPI flash for configuring, but not all chips may be supported by the maker's programming software. You could program with other software but it could be a little more fiddly.
 

[tszaboo]

The Max 10 is absolutely the next chip I'm most excited about. It's what they should've made the next Cyclone (instead they backported the stratix arch to the cyclone series and bumped the min price)
Unfortunately I can't tell you about all the cool aspects of the MAX10 due to NDA but the silicon is just getting out there and it is very well suited for the lowcost area. It's basically the good ol' Cyclone arch on 55nm
They even provide a QFP package option.

55 nm CPLD ( lil'FPGA )? I can only hope they can fit the bigger devices into that QFP package, not one of these joke size 32 MC ones.

[marshallh]

55 nm CPLD ( lil'FPGA )? I can only hope they can fit the bigger devices into that QFP package, not one of these joke size 32 MC ones.

There is nothing CPLD about it. Like I said before it is the Cyclone arch with some other stuff integrated onto a smaller die and with smaller/denser package options. It is for all intents and purposes a FPGA

[Scrts]

55 nm CPLD ( lil'FPGA )? I can only hope they can fit the bigger devices into that QFP package, not one of these joke size 32 MC ones.

There is nothing CPLD about it. Like I said before it is the Cyclone arch with some other stuff integrated onto a smaller die and with smaller/denser package options. It is for all intents and purposes a FPGA

MAX10 will be FPGA. It will support DDR2/DDR3 memories (Cyclone IV doesn't) and will be capable of running Nios.

Be aware guys of Platform L. But now -