FPGA configuration

[fagiano]

Hi,
I'm designing a board with a Xilinx FPGA and I'm scratching my head on how to setup the bitstream configuration.
I'd like to have 3 programming modes:
 *an SPI flash in master mode(the FPGA sucks the bitstream from it at startup)
 *being able to program the bitstream from the MCU that will also be on the board
 *JTAG for developing
Now I think I understand how to do both the SPI and MCU options, but for what I can see I'll have to share the SPI pins on the FPGA.
My problem is that I'm not sure how to isolate the MCU or the SPI flash when one or the other is not used.
I'm quite a newbie in electronics, so far the only thing I can think of is to pass both SPI interfaces through two separate 3-state buffers(74LVC125A) and put in high impedance mode(from the MCU or jumper) when I want to isolate the interface connected to it.

Am I missing something? Is there a better way?
Also I assume the JTAG will be able to program the SPI from Impact, right?

thank you for your time

ciao
Alberto

PS: I also plan to have a jumper to set the FPGA mode.

[jeroen74]

So far I know... the FPGA tristates the SPI lines to the SPI Flash after it has read out the contents of it; the DONE pin indicates this. The MCU can then take control. If you keep PROG_B low you can stop the FPGA from reading the Flash.

You can program the SPI flash from Impact; it basically downloads a small FPGA configuration first that funnels the data from JTAG to the SPI.

All these little details are the configuration guide of the FPGA family you are using

[fagiano]

Thank you, I missed the fact that the pins go into high impedance after the programming is done. I went though the configuration reference but
but I'm just starting with electronics, so for me this kind of documents are a lot to chew .

Anyway, do you mean that I don't have to isolate the MCU data/clk pins from the flash ones? The MCU defaults to "input floating" on reset.

Alberto

[jeroen74]

Yes, with all those different possible configuration methods it's not for the faint hearted

Yes, I see no reason to add extra hardware as long you can tristate the MCU pins.

[marshallh]

As always the solution is to RTFM.... Find what volume of the documentation deals with it, and read ALL of it
Only way to not bake a coaster pcb...

[fagiano]

Thank you again jeroen74, I'll give it a try.

marshallh i did RTFM, as I stated, but as I'm a newbie I was looking for validation on what I've got from it. So thank you too for the wise advice .

ciao
Alberto

[mikeselectricstuff]

As well as TFM, look at schematics of development boards for details of config stuff (but bear in mind some may provide for more options than you need)

[Hardcorefs]

Hi,
I'm designing a board with a Xilinx FPGA and I'm scratching my head on how to setup the bitstream configuration.
I'd like to have 3 programming modes:
 *an SPI flash in master mode(the FPGA sucks the bitstream from it at startup)
 *being able to program the bitstream from the MCU that will also be on the board
 *JTAG for developing
Now I think I understand how to do both the SPI and MCU options, but for what I can see I'll have to share the SPI pins on the FPGA.
My problem is that I'm not sure how to isolate the MCU or the SPI flash when one or the other is not used.
I'm quite a newbie in electronics, so far the only thing I can think of is to pass both SPI interfaces through two separate 3-state buffers(74LVC125A) and put in high impedance mode(from the MCU or jumper) when I want to isolate the interface connected to it.

Am I missing something? Is there a better way?
Also I assume the JTAG will be able to program the SPI from Impact, right?

thank you for your time

ciao
Alberto

PS: I also plan to have a jumper to set the FPGA mode.

The JTAG overrides all others.
You  use the mode select pins to configure other modes.

go check out the xilinx 'targeted'  white papers there is a range of solutions carefully laid out , also go pull some schematics to see how other implement the re-use of pins

[Crazy Ape]

How big is the MCU involved, or perhaps, how much free space is on it would be the better question?

A design I was toying with, and will get back to (it works well) uses the MCU to read an xsvf file from SD card and configure the FPGA directly through the JTAG pins.
I used ChaN's FAT to handle the SDcard and xsvf player to program the FPGA via JTAG.
In this case I used an NXP LPC1768 as the MCU and I was programming a Xilinx XC3S200A FPGA.

If your project already has SDCARD support then you're already half way there.

'Sprites mods' takes this idea to the extreme (no SDcard or FAT support though) using an ATTiny85 microcontroller here:
http://spritesmods.com/?art=stdalonejtag&page=1

[fagiano]

The MCU is big, is an STM32F407Z with 1MB of flash. I was thinking of adding a 1Gbit of nand flash as my sd card pins are already used but I'll leave that for a future revision as doing the PCB layout with two 144QFP components is already redefining my meaning of tedious .

mikeselectricstuff: I looked at the schematics of a devboard with similar MCU+FPGA and that is what got me insecure/confused, they are using some electronic switch and tristate between the flash/MCU/FPGA (PS: I'm a big fan of you channel).

For now I'll try to just share the pins as jeroen74 suggests, if it doesn't work, I'll just have to try again.

Thank you all for the advice.

ciao
Alberto

[Crazy Ape]

The MCU is big, is an STM32F407Z with 1MB of flash. I was thinking of adding a 1Gbit of nand flash as my sd card pins are already used but I'll leave that for a future revision as doing the PCB layout with two 144QFP components is already redefining my meaning of tedious .

I'm waiting on a STM32F407IGT6 to arrive in the mail, very similar device.

[free_electron]

doing the PCB layout with two 144QFP components is already redefining my meaning tedious

You call that tedious ? I call that half an hour of fun. I did one yesterday ( and the day before) with a 208 pin qfp, a 144 qfp and three tsop48 memories... And a bunch of level translators 74vhcx4245) in tssop . Had to fit in 6x10 cm... Absolute fun. I did it on 2 1/2  routing layers  short hops are interspersed on the powerplane, he ne the 1/2 layer

[mikeselectricstuff]

doing the PCB layout with two 144QFP components is already redefining my meaning of tedious

Not usually a big deal with FPGAs as there is so much scope to juggle pins around to make the PCB easier, unless you have multiple bank voltages, when things can get more constrained.
Most of my FPGA designs have been on 2 layer PCBs, including a QFP144 driving two LCDs & a NAND flash

[fagiano]

The last 2 posts make me wonder about my layout methodology  , I have to route the memory controller pins from the MCU to the FPGA. That is about 40 pins scattered on 4 sides of the microcontroller and I'm trying to put the address bus all on the same bank of the FPGA(is this necessary? I guess so, not sure), this is cross cutting both my top and bottom layers in 2 and I'm having big troubles routing all the rest (USB phy, LCD, and power, io). Should I redesign my board so is easier to layout(connect to different banks) or should I just keep it as it is and go nuts with vias? The major issue for me is finding some documentation on PCB layout than is neither trivial arduino-class or advanced stuff like DDR3, just figuring out when a via is acceptable. All this papers about vias inductance made quite paranoid on hopping through layers. I'm pretty much guessing on my own and I feel bad on posting 1000 trivial questions on forums. In the past I did some incredibly educational PCB, one had so much crosstalk on a sound chip that it could almost be considered a wireless transceiver (that is how I learned about return currents, and ground planes) Is there some source to learn this kind of stuff or should I just stick on trial and error(and staring at devboards)?

Alberto

[larry42]

Is there some source to learn this kind of stuff or should I just stick on trial and error(and staring at devboards)?

Four years of university and a decade in industry helps... I think you might be starting a bit too big. How many pins are your devices and how many layers is your PCB?

[fagiano]

two 144TQFP, one 48TSOP, one 32QFN, two 10MSOP. Two or Four layers I'm experimenting with both but four layers looks easier. I did few boards before with smaller MCUs and CPLDs, I want to step up one level. I bought my first breadboard about 1 year ago.

Alberto

[jeroen74]

Maybe it helps to post a screenshot of your PCB.

[fagiano]

I did a lot of practice in the last few days by trying to layout one chip to the MCU at the time rather than trying to do all the board at once. I'm starting to get a grip on the whole PCB layout, my biggest problem was IC placement. I think I just have to take a deep breath and power though it with trial and error.

thanks for the help I'm sure I'll be back before I'm done with this board

ciao
Alberto

[Crazy Ape]

I see lots of boards that have high pin-count devices placed at a 45 degree offset, this helps with routing to other high pin-count devices as you have two sides of the device exposed in any direction for routing. Something to consider if you haven't already.